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Atrenta Testimonials
"The timing and physical closure of our SoCs has always been a big challenge for us. We needed a tool that would partition our SoCs based on our requirements, and provide trade-off analysis and guidance for our implementation tools. The SpyGlass Physical product was able to achieve just that on 40nm and 32nm SoCs in significantly shorter time than we expected..."
François Rémond
Director of CAD
STMicroelectronics
"Atrenta's SpyGlass CDC product is critical in helping us avoid design iterations and general risks associated with our complex designs. We have been very impressed by the comprehensive solution offered by SpyGlass CDC, which allows us to quickly identify real problems in our clock networks at the earliest possible point in the design flow..."
Raimund Soenning
Manager Hardware Development - Graphics Competence Center
Fujitsu Microelectronics Europe
"Atrenta's SpyGlass platform has been instrumental in helping us reach the stringent quality goals we set for our broad IP portfolio."
Chandan Egbert
Senior Director of Engineering
Arasan
"We are very impressed with the capabilities of SpyGlass Power for RTL power estimation and verification - both with and without simulation vectors. The RTL power estimation results with simulation vectors for clock, data-path and memory were within 20% of final silicon numbers."
Nobuyuki Nishiguchi
Vice President and General Manager
STARC
"By using SpyGlass Power for RTL level analysis and efficient clock gating, we were able to reduce power by up to 40% in our wireless chip." Akira Denda
Department Manager, Device Platform Development Department 1st SoC Operations Unit
NEC Electronics Corporation
"Atrenta's SpyGlass CDC product allows us to ensure correct clock synchronization in our complex ASIC and FPGA designs. We have deployed SpyGlass CDC as a mandatory part of our ASIC and FPGA design flows to verify correct synchronization as early as possible."
Yuji Yoshitani
Senior Engineer
Fujitsu Kyushu Network Technologies System Logic Development Center
"In our evaluations, we found that the SpyGlass Constraints SDC equivalence capability allowed us to identify and fix a range of issues… We view constraint verification as a continuous process - it is essential to be able to verify block level constraints in the context of a chip..."
Nobuyuki Nishiguchi
Vice President and General Manager
STARC
"(STMicroelectronics) had been looking for a design environment … focusing initially on architectural-level power analysis, estimation and management, and subsequently on top-down timing budgeting. We were very happy to discover a clear vision match with Atrenta's GenSys™ product."
Philippe Magarshack
Vice President for Central CAD & Design Solutions
STMicroelectronics
"Our advanced digital television chips require automated assembly and sophisticated I/O support. We are pleased with the results we have seen so far using Atrenta’s GenSys. We plan to use the product for automated assembly and I/O configuration on our latest designs."
Dr. Kang, Yong-Seok
Principal Engineer of Design Technology Part
LG Electronics
"The use of Atrenta SpyGlass for DS2 product development facilitates early bug detection and enhances the reliability and quality of the final ASIC, allowing us to design the best product for our customers… These products help us to achieve excellent results regarding development time, quality of the final ASIC and overall development cost."
Javier Jimenez
ASIC Design Manager
DS2
"By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process…The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized."
Shawn McCloud
Product Line Director for High-Level Products
Mentor Graphics Corporation
"The integration of Atrenta’s SpyGlass MBIST solution in our front-end design kit has automated ST’s proprietary embedded memory test and repair capabilities at RTL. The solution not only allows early and faster validation at RTL, but also allows timing optimization of the complete RTL with memory BIST where area impact is known early.”
Frederic Grandvaux
Memory Test Solutions Manager within Central CAD & Design Solutions
STMicroelectronics
"We have three designs in advanced phase of development that rely on inserting memory test with the SpyGlass MBIST solution. This automatic solution becomes necessary in devices having huge proliferation of memory instances, as our applications require improving efficiency/lead time in our DFT design flow.”
Angelo Oldani
Design Director for the Communication Infrastructure Division
STMicroelectronics
"… This collaboration with Atrenta makes it possible for SoC architects to explore feasibility of their architecture and then dial-in the parameters and generate an appropriate Databahn™ configuration. This is powerful stuff."
Marc Greenberg
Director, Technical Marketing
Denali Software
“The Atrenta SpyGlass CDC product provides detailed clock domain synchronization checking, useful for external IP and IP integration verification. We are pleased to adopt this EDA tool to assist us with product development efficiencies."
Rick Bahr
Vice President of Engineering
Atheros
“Forte's Cynthesizer™ and Atrenta's SpyGlass are integral parts of the SystemC-based ESL deployment flow found in many of the top ten systems and semiconductor companies around the world. Our silicon proven joint solution increases productivity and overall design quality while minimizing risks for both control and datapath designs."
Brett Cline
Vice President of Marketing and Sales
Forte
"Atrenta's SpyGlass enables us to gauge quickly the quality of incoming RTL designs from our customers, reduce risks (e.g. effort and time) and then plan project resources and timelines accordingly. For our complex SoC designs, the clock domain crossing (CDC) capabilities in SpyGlass have proven to be mission critical. “
Rudolf Krumenacker
Head of Embedded Systems Design
Tieto
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