The trends toward convergence in applications on a single SoC and increasing design costs, are driving design teams to explore IP reuse and platform-based design techniques to improve overall design efficiency and ROI.

In this demo, you will see how Atrenta's 1Team-Genesis platform provides a structured SoC assembly methodology that enables IP re-use, IP import, automated connectivity generation, registers management, early power planning and power management, I/O planning and generation, early physical planning and topology generation.

A variety of design risks related to structure, timing, test, clocks and power result in design iterations and, even worse, silicon re-spins. In addition, design re-use and IP integration require guidelines for correctness and consistency.

In this demo, you will see how to uncover critical design issues not covered by independent analysis and accelerate design closure associated with structure, timing, test, clocks, area, routing congestion and power, using unified methodology in the SpyGlass® platform that reduces the number of independent analysis steps.

Want to learn more? We have focus sessions to meet your needs. These sessions provide detailed discussions on specific portions of Atrenta's flow as well as several business initiatives.

SpyGlass Platform Focus Sessions

Late discovery of chip limitations (timing, area, power tradeoffs) cause iterations and schedule delays. The SpyGlass-Physical solution provides early visibility and feasibility analysis related to physical characteristics at RTL, enabling designers to make local changes to the code and complete verification before handoff to implementation.

You will never close timing without good constraints. The SpyGlass-Constraints solution takes the risk out of timing closure with comprehensive support for the management and verification of design constraints, including false and multi-cycle paths.

Are you risking bad silicon? Some of the most common reasons for silicon re-spins today are synchronization issues due to asynchronous clock domain crossings (CDC). Traditional methods like static timing analysis and simulation often do not identify these hard-to-detect bugs. The SpyGlass-CDC solution enables you to identify clock domain crossing issues at RTL or netlist and ensure that clock synchronization is correct.

The SpyGlass-Power solution provides comprehensive, estimation-driven power reduction and broad power verification - from RTL to post-layout, supporting both UPF and CPF. Low power-aware design requires the designer's attention from the first architectural decisions all the way through to final layout. The designer needs to explore as many architectural tradeoffs that are feasible, and requires fast, accurate determination of the power at all stages of the design flow. Hence, there becomes a growing need for power verification checks to ensure that power intent is still being met throughout the design flow - from RTL to post-layout.

The SpyGlass-DFT solution is an industry-leading product to address testability in hours during RTL design instead of days later in the design cycle. The solution enables RTL designers to create testable designs without becoming test experts and achieve high coverage (98-99%). Atrenta's at-speed test solution, SpyGlass-DFT DSM, addresses the latest deep submicron challenges for test. Our new memory built-in self test (MBIST) solution, SpyGlass-MBIST, provides insertion automation and validation of vendor independent BIST IPs at RTL.

Complexity and cost of today's SoC's is driving an increasing trend toward IP and subsystem re-use, which further exacerbates the challenge of integrating IPs from different sources.  Atrenta's 1Team-Genesis product enables a structured SoC assembly methodology that enhances the efficiency of your design flow by enabling a seamless IP reuse and automated SoC integration methodology.  Automatic connectivity generation boosts designer productivity significantly and at the same time helps eliminate manual errors.

Key technical topics in this focus session include IP/design import, automated connectivity generation, hierarchy manipulation, automated I/O pin-mux generation based on specs, the infrastructure to automate the generation of other key architectural subsystems (such as clocks, DFT, reset etc.) and finally a structured documentation interface to read in from and write out to design docs.

The increasing trend towards mobile applications and the green revolution is driving design teams to start looking at low power techniques from the earliest stages of their design flow.  Atrenta's 1Team-Genesis power solution provides visibility into the power profile of a design at the architectural stage. It also helps designers explore various tradeoffs to reduce power and helps them capture the final power intent through industry-standard UPF/CPF files that can be handed seamlessly to downstream implementation tools.

Key technical topics in this focus session include power profiling, what-if analysis to explore tradeoffs during early power domain planning, use of advanced techniques such as retention and DVFS, exploring the physical impact of power architecture and finally, capturing the detailed power architecture.

With the increasing emphasis on software content as a differentiator for SoC platforms, it is becoming increasingly difficult for design teams to ensure that the hardware and software teams remain in sync and can progress in lock-step.  Atrenta's 1Team-Genesis Registers solution alleviates this concern by providing an IDE that helps streamline a design flow without disrupting existing processes. As a single source for IP selection, configuration and integration, this solution enables complete automation of the hardware-software interface ensuring data synchronization, as well as improving interoperability and communication between design teams and tools. 

Key technical topics in this focus session include IP and system creation and import, creation and management of a components memory map, registers and bit-fields, as well as the auto generation of synchronized design views such as RTL, software APIs and documentation. A live demonstration of the product will also be provided.

If you are someone who wants to improve design efficiency, quality and reduce cost, you will not want to miss this focus session. The session will highlight how Atrenta's Early Design Closure solutions can be deployed to measure design quality, quantify design risk, automatically generate and track key design metrics, and help manage the SoC development life cycle effectively.

The move toward stacked die 3D design is undeniable. This promising new technology will shape new product development for years to come. The challenges of designing in a 3D world are daunting, and will require fundamentally new approaches to design planning and analysis.

Atrenta, AutoESL, IMEC and Qualcomm are working together to develop a comprehensive top-down design flow to address the challenges of this emerging technology. In this session, we will take you through a live demonstration of the design of a 3D stack, including high-level synthesis, partitioning, floor planning and analysis.

When & Where
Wednesday, June 16, 2010
1:30 PM — 2:30 PM
2nd Floor Foyer Adjacent to 208AB

10U.1 P— An RTL approach to Memory BIST insert with Proprietary Architectures

Speaker
Marcello Raimondi - STMicroelectronics, Milano, Italy

Authors
Marcello Raimondi - STMicroelectronics, Milano, Italy
Alberto Carava' - STMicroelectronics, Milano, Italy
Frederic Grandvaux - STMicroelectronics, Crolles, France

When & Where
Thursday, June 17, 2010
1:30 PM — 2:30 PM
2nd Floor Foyer Adjacent to 208AB


10U.25 P— A Methodology for Automatic Generation of Register Bank RTL, Related Verification Environment and Firmware Headers

Speaker
Bhawna Chopra - STMicroelectronics, Noida, India

Authors
Saurin Patel - STMicroelectronics, Noida, India
Mukesh Chopra - STMicroelectronics, Noida, India
Bhawna Chopra - STMicroelectronics, Noida, India

When & Where
Thursday, June 17, 2010
1:30 PM — 2:30 PM
2nd Floor Foyer Adjacent to 208AB