In This Issue
- New EDA Tools Improve Low Power Design
- Si2's Low Power Coalition Receives Common Power Format Parser Source Code
- Atrenta Donates Low Power Constraint Format to Accellera
- Atrenta Gains Key Patents for Chip Design Analysis Technologies
- NEW!! White Paper: Low Power Design: Approach and Techniques for Power Estimation, Reduction and Verification
- Workshop on SpyGlass-Power
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| New EDA Tools Improve Low Power Design |
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Ten years ago, power was a minor concern for many IC designers. Today, four in five chips have a power budget below 2W. The emphasis on low power is due in large part to the explosion of compact mobile systems, but also to the need to reign in the overall power consumption of large-scale systems such as servers and switches. Click here for more |
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| Si2's Low Power Coalition Receives Common Power Format Parser Source Code |
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"Atrenta welcomes the contribution of a CPF parser to the SI2 Low Power Coalition," said Ajoy Bose, president & CEO of Atrenta. "We are actively participating in driving power standards so our customers benefit from a simple industry-wide low-power design flow. Availability of this reference implementation parser will ease the addition of CPF support to our SpyGlass Low Power and Power Estimation products." Click here for more |
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| Atrenta Donates Low Power Constraint Format to Accellera |
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Atrenta donated its SpyGlass Design Constraints (SGDC) for low power design to Accellera's Unified Power Format (UPF) Technical Subcommittee.
Atrenta's constraint format enables IC designers to specify design intent for voltage domains and power isolation domains. The format also supports advanced low power techniques at various phases of the design, including RTL, post-synthesis and post-routing. Click here for more |
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| Atrenta Gains Key Patents for Chip Design Analysis Technologies |
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Strengthening its leadership position in early design analysis tools, Atrenta has been awarded five new patents by the U.S. Patent Office for significant chip design analysis technologies. The low power design technologies patented provide SpyGlass-Power with capabilities such as identification and implementation of clock gating in IC design to reduce dynamic power consumption, and automatic insertion and verification of level shifter modules used in integrated circuits. Click here for more |
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NEW!! White Paper
Low Power Design: Approach and Techniques for Power Estimation, Reduction and Verification |
| The battle against power consumption is nothing new and the designers have a number of ways to decrease power consumption including using lower supply voltages and taking advantage of power management features wherever available, as well as specific programming techniques for reducing power consumption. Click here to get your copy |
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| Workshop on SpyGlass-Power |
| This workshop focuses on Power Estimation, Power Reduction and Power Verification to ensure power-efficient designs. Click here to register for the workshop |
