In This Issue
- Cray Adopts Atrenta's SpyGlass Platform
- FREE White Paper: Do your Chip a Favor! Manage the Constraints!!
- Workshop on SpyGlass-Constraints
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| Cray Adopts Atrenta's SpyGlass Platform for Next Generation ASIC Projects |
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Cray, the global leader in supercomputers, has adopted the SpyGlass platform for the company's next generation ASIC projects. Using the SpyGlass platform, including SpyGlass-Constraints and SpyGlass-DFT, Cray's design teams managed to address critical issues early at RTL on a 30M gate design, thus preventing a domino effect of delays & iterations later in implementation & verification phases. Click here for more |
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FREE White Paper
Do your Chip a Favor! Manage the Constraints!! |
| Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle. However, there is no validation step for the constraints prior to their use in the implementation/validation tools, like synthesis, static timing analysis or place & route. Click here for more |
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| Workshop on SpyGlass-Constraints |
| SoC development involves the validation of constraints at various stages, such as RTL, pre-layout, and post-layout. Resolving constraint inconsistencies between the block and chip levels, between pre-synthesis, pre-layout, and post-layout is highly critical for the timely development of SoC and superior quality of the results. This workshop demonstrates how SpyGlass-Constraints can help achieve this goal of predictive development of your SoC designs. Click here for free registration |
