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In This Issue - Atrenta Launches Customer Workshop Series - Low-Power Design: Implications and Options - Estimating Fault Coverage from RTL without Fault Simulation - Atrenta Awarded DFT Patent - 1Team:System Available for Production Use - Atrenta Strengthens Presence in Japan - Predictive Development Demos at DATE 2006 - A Systematic Approach to Verifying FSMs |
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Atrenta Launches Customer Workshop Series Atrenta kicked off a series of half-day customer workshops with sessions on design for test (DFT) and low power analysis. The upcoming workshops, to be held at Atrenta's training center at San Jose and customer sites worldwide, will cover a wide range of topics including SpyGlass, predictive RTL hand-off, clocks and constraints. Upcoming hands-on workshops: - SoC Design Flow: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in 1Team:Analyze (formerly SpyGlass). - 1Team:Analyze (SpyGlass) - Clocks: This workshop introduces the clock and reset analysis capabilities in 1Team:analyze and SpyGlass Design Constraints (sgdc) files for use in clock-reset analysis. - 1Team:Constraint (SpyGlass Constraints): SoC development involves the validation of constraints at various stages, such as RTL, pre-layout, and post-layout. Resolving constraint inconsistencies between the block and chip levels, between pre-synthesis, pre-layout, and post-layout is highly critical for the timely development of SoC and superior quality of the results. This workshop demonstrates how 1Team:Constraint can help achieve this goal of predictive development of your SoC designs. - 1Team:Analyze (SpyGlass): This training course introduces the predictive analysis capability of 1Team:Analyze. It explains the use of the product in various methodologies in the RTL-handoff process, such as Audit, Block-Design, and RTL-Handover. Sign-up for one or more workshops and stay current on Atrenta's predictive development solutions. For more information about these free workshops and to register, please contact your account manager or Sean O'Kane (moreinfo@atrenta.com). Estimating Fault Coverage from RTL without Fault Simulation Fault coverage is a critical measure for evaluating the effectiveness of manufacturing test programs. Typically, actual coverage is determined by fault simulation tools at the end of the process flow. The ATPG step involves generating a test for a specific fault and then simulating that test for both the fault free behavior and the behavior for all undetected faults. If the values at circuit outputs for any of these undetected faults are different from the expected output for the fault free circuit, then that fault is declared detected. The process continues until as many faults as possible are detected. Click here for a free white paper. |
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 Atrenta Awarded DFT Patent “Method for Determining Fault Coverage from RTL Description” Awarded Atrenta has been awarded a U.S. patent for determining fault coverage from RTL description. This technology is integrated in Atrenta’s 1Team RTL desktop for predictive development that enables users to identify, analyze, debug and fix design issues in RTL, and hence avoid late stage design surprises. By accurately predicting the fault coverage at the RTL, the designers can easily affect and simulate the DFT changes. The RTL can be maintained as the golden file, so that any reuse will also have high test coverage. The accurate test coverage feedback and incremental priority information allows the users to focus on test problems that have the highest impact on coverage. Low-Power Design: Implications and Options Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost. Click here for a free white paper. 1Team:System™ Available for Production Use 1Team:System is available for production use. 1Team:System is a comprehensive hardware and software analysis tool for electronic system-level design that reduces system implementation costs, while ensuring that SystemC code accurately models system-level objectives. 1Team:System has been adopted by industry-leading Japanese semiconductor companies, as a critical portion of their SystemC design flow aimed at  reducing time to market while at the same time managing SoC complexity - resulting in an increased performance and functionality for the company’s products. 1Team:System can significantly accelerate adoption of SystemC across a broader user-base than has historically been feasible. The potential for high-level modeling, design and verification can only be fully realized by extending access to non-experts, which requires tools to help those users become proficient quickly. 1Team:System provides automated best practice analysis and readily understood diagnostics - the most important first step for users making the transition to ESL. Atrenta Strengthens Presence in Japan  Atrenta has set-up its wholly owned Japanese subsidiary, Atrenta KK as an important step in our strategy to bring products and solutions even closer to our customers around the globe. Japan is a strategic market for predictive design automation.Atrenta KK showcased a line-up of its predictive development products - 1Team platform - at Japan's Electronic Design and Solution Fair (EDSFair) in Jan 06 at Yokohama, Japan. In addition to presentations held at its booth, Atrenta delivered seminars on predictive development, clocks, constraint, DFT, and SystemC. Atrenta’s booth attracted considerable interest from several industry-leading Japanese semiconductor companies.  Atrenta Showcases Predictive Development Technology at DATE 2006Atrenta will showcase its next-generation of SpyGlass™ tool suite, called 1Team™, at the upcoming DATE Mar 7-9, 2006, in Munich, Germany. Product demonstrations at Atrenta’s booth #A14 range from predictive analysis tools to automatic constraints management and formal verification to the hardware/software analysis for electronic system-level design. |
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| To book an appointment for a private demonstration, please email Charu Puri at cpuri@atrenta.com. | |||
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Hercules Provides $10.0M Financing to Atrenta Hercules Technology Growth Capital, Inc. (Nasdaq: HTGC - News), a leading debt and equity growth capital provider to technology and life science companies announced that on Dec. 30, 2005 it provided $10.0 million of structured mezzanine debt financing to Atrenta Inc. Funds will be drawn upon as needed to accelerate the company's growth. Click here for more. Articles A systematic approach to verifying FSMs - By Shaker Sarwary, Atrenta, and Michael A Beaver, Insilica – EDN Where are the tools for next node? - EE Times design automation editor Richard Goering interviews Philippe Magarshack, group vice president for central R&D at European semiconductor giant STMicroelectronics, the ST executive had plenty to say about EDA tool requirements, gaps in the design flow, the daunting challenges of 45 nm, the future of systems-on-chip…EETimes |
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About Atrenta Atrenta Inc. is the leading provider of Predictive Development, a new class of integrated circuit design automation solution that turns the costly and error-prone activity of SoC development into a more predictable, manageable and reliable process. Atrenta has over 100 customers worldwide, including 9 of the world's top 10 semiconductor companies. For more information, please visit www.atrenta.com. © Copyright 2006 Atrenta Inc. SpyGlass, 1Team:Analyze, 1Team:Analyze Power, 1Team:Analyze Test, 1Team:Constraint, 1Team:Verify, 1Team:Implement, 1Team:System are trademarks of Atrenta Inc. All trademarks mentioned herein are the property of their respective owners. This message was sent by Atrenta Inc., 2077 Gateway Place, Suite 300, San Jose CA 95110 USA. Click here if you prefer not to receive future e-mail from Atrenta Inc. |
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