In This Issue   - RTL++ and the Return of the Tall Thin Designer   - STMicroelectronics Standardizes on Atrenta's Early Design Closure Solution   - Solving the Toughest Problems in CDC Analysis   - Early Design Closure Workshops and Seminar!   - Designing for test at RTL   - Atrenta Secures $16M in Series D Funding RTL++ and the Return of the Tall Thin Designer A new and broader definition of register-transfer level (RTL) design is emerging that puts new demands on logic designers and creates new opportunities for designers to add value and distinguish themselves. Click here for more     STMicroelectronics Standardizes on Atrenta's Early Design Closure Solution STMicroelectronics has standardized on Atrenta's early design closure solution as part of a company-wide front-to-back design methodology. The deployment of Atrenta's solution at ST, a global semiconductor giant, includes the complete Spyglass solution, together with the ST Design Convention best practices. Click here for more     Solving the Toughest Problems in CDC Analysis FIFO and Handshake Synchronizers Pose Special Difficulties; New Tools Are the Answer Among the many verification challenges confronting system-on-chip (SOC) designers these days, clock domain crossings (CDCs) rank near the top in difficulty. The latest SoCs may have dozens or even thousands of clock domain crossings, many of them difficult to verify using conventional tools such as simulation. For these bugs to be detected in simulation it requires long simulation runs and a chance encounter. As a consequence, CDCs have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly re-spins. Click here for more     Designing for test at RTL Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses. In the early design stages, the design focus is on meeting system requirements so it is often the case that DFT issues are not addressed until much later in the process flow. Various products have been developed for DFT checking on post synthesis or gate level netlists but they are specific to particular tools and therefore often do not support user specific or custom requirements. Even more importantly, these post synthesis techniques do not provide any easy means to update the RTL when DFT changes are required. Click here for your copy of the white paper     Events Calendar Upcoming hands-on workshops: Sign-up for one or more workshops and stay current on Atrenta's early design closure solutions. - SpyGlass-CDC: This workshop introduces the clock and reset analysis capabilities in SpyGlass and SpyGlass Design Constraints (sgdc) files for use in clock-reset analysis. - SpyGlass-Low Power: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in SpyGlass. - SpyGlass-Constraints: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in SpyGlass. - SpyGlass-DFT: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in SpyGlass. Upcoming hands-on trainings: - General SpyGlass Training: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in SpyGlass. - SpyGlass Builder Training: This workshop demonstrates how to execute predictive RTL hand-Off using design methodology templates and interactive debugging available in SpyGlass. Register Here Atrenta Secures $16M in Series D Funding Atrenta, the leading provider of broad-based design analysis solutions with the industry standard SpyGlass technology, has successfully secured $16 million in new equity financing. Investor Growth Capital led the financing in this Series D round. Samsung Ventures and Hercules Technology Growth Capital, Inc. joined existing investors, Venrock Associates, TL Ventures, Smart Technology Ventures, Investcorp Technology Ventures and Finaventures, in the financing round. In conjunction with the financing, Jose Suarez of Investor Growth Capital has joined Atrenta's Board, and Bill Byun of Samsung Ventures joins as an observer on the Board. The funds will be used to fuel the company's continued growth by expanding Atrenta's product offerings in chip design software and its worldwide presence for sales and support. Click here for more About Atrenta Atrenta Inc. is the leading provider of broad-based design analysis solutions based on industry standard SpyGlass™ technology. Atrenta's design analysis tools deliver early design closure by eliminating downstream design problems and iterative discoveries. This leads to improved predictability and efficiency in SoC design phases including RTL design, IP reuse, Verification, logical and physical implementation. Atrenta has over 100 customers including the world's top 10 semiconductor companies - Think Early Design Closure, Think Atrenta! www.atrenta.com. © Copyright 2006 Atrenta Inc. Early Design Closure, SpyGlass, SpyGlass-Low Power, SpyGlass-DFT, SpyGlass-Constraints, SpyGlass-CDC, 1Team-Implement, 1Team-System are trademarks of Atrenta Inc. All trademarks mentioned herein are the property of their respective owners. This message was sent by Atrenta Inc., 2077 Gateway Place, Suite 300, San Jose CA 95110 USA. Click here if you prefer not to receive future e-mail from Atrenta Inc.