In this Issue Design Quality Enhances Company Survival Experts at the Table: Platform-Based Design Performance or Time to Market. What's Your Choice? Streamlining IP-based Chip Design Hear about Atrenta’s efforts to improve IP quality Mike Gianfagna, VP of Marketing at Atrenta, Speaks at DesignCon 2009 SpyGlass® Workshop Free White Paper: SpyGlass® Application in an FPGA to ASIC Conversion Atrenta in DAC User Tracks


News and Articles

		Design Quality Enhances Company Survival by Bernard Murphy Most projections for 2009 show IC sales shrinking more than 10 percent. Six of the top ten companies are expected to see a decline in revenue. Some have predicted 40 percent of IC companies will either disappear or be absorbed into more successful competitors over time. In this climate, flawless execution is no longer a visionary goal " it has become a basic survival skill. Read More



		Experts at the Table: Platform-Based Design by Ed Sperling System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation. Excerpt: Answering to a question, Mike Gianfagna of Atrenta said, "We have a customer now with 20 power domains. Of those 20, there are hundreds of ways you can slice them. Which one is right? There is a lot of 'What If' going on. Maybe you do a trial through a high-level synthesis through a synthesis down through RTL, and then go back and try it again. The good news is I can do that in days. If I go down to the gate level, it's weeks. You've got to do these 'What ifs' at the higher level. New tools-some exist, some are still to be invented and released-are the only way to get there." Read more: Part 1 \| Part 2 \| Part 3



		EDN Blog: Performance or Time to Market. What's Your Choice? How much theoretical performance are you willing to give up to tape out your design and get it into silicon? It's truly a practical question. Engineers intuitively know that the closer they try to get to perfection, the longer it takes. Push silicon technology hard to get clock speed or low power and you'll spend a lot of time chasing the problems that crop up. Read More



		Streamlining IP-based Chip Design by Piyush Sancheti IP quality is a hotly debated topic in the semiconductor industry with many aspects and varying perspectives, depending on whether you are a supplier or a consumer. Read More



		Atrenta in DAC User Tracks Come to DAC 2009 and hear customer success stories using Atrenta's advanced technologies: USER TRACK: Towards Front-End Design Productivity 6.3s Assessing Design Feasibility Early with Atrenta's 1Team®-Implement SOC Speaker: Thierry T. Sejourne - STMicroelectronics, Grenoble, France USER TRACK: Front-End Power Planning and Analysis 9.3s New SOC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs Speaker: Sarveswara Tammali - Texas Instruments, Inc., Bangalore, India USER TRACK: Front-End Power Planning and Analysis 9.5 ALPES: Architectural-Level Power Planning and Estimation Speaker: Francis Maquin - STMicroelectronics, Crolles, France




	Mike Gianfagna, VP of Marketing at Atrenta, Speaks at DesignCon 2009 Click here for video


	Hear About Atrenta’s Efforts to Improve IP Quality


	SpyGlass 4.2.0 Webinar We have received an overwhelming response to the SpyGlass 4.2.0 webinar from our users. The repeat live broadcast will take place on May 13 , 2009. Watch your inbox for more details and the schedule for this event.


	SpyGlass® Workshop This workshop introduces users to the predictive analysis capability of SpyGlass. The use of SpyGlass in the various methodologies in the RTL handoff process such as audit, block-design and RTL-handover are explained in this workshop. Request additional information


	Free Whitepaper SpyGlass Application in an FPGA to ASIC Conversion Mapping an FPGA design to an ASIC can be a problem-free experience if the FPGA was designed from the outset with a re-map in mind. If you did not take this precaution, you may find that so many changes are required to make the FPGA RTL ASIC-compliant that you must effectively re-design and re-verify the RTL. In this case, the FPGA implementation becomes little more than an existence proof that a working implementation can be built. By following the Atrenta GuideWare™ methodology using the SpyGlass® family of tools, you can achieve portability of the design from the FPGA implementation to the ASIC implementation, and from one process node to the next. Atrenta's GuideWare methodologies contain a comprehensive set of checks and qualified templates that allow for maximal portability of the design. Click here to get your copy

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! www.atrenta.com .

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