The key element of a successful IP block is being able to seamlessly integrate into a larger design, especially with the myriad of internal buses. Seamless integration demands that the interface IP deliverables come with support that understands the SoC's operation in the final consumer application.
For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff.
A combinational loop is formed when a signal can reach back to itself without encountering any sequential device in the path. Typically, besides the signals that form the loop, some other signals
would also be entering the segments that form the loop. The outputs of some of the segments could also be going elsewhere—outside the loop.
As SoC designers start wrestling with smaller and smaller process geometries and increasing functionality on a chip, they’ll be using more and more third party IP. We all know that. But the future of coming SoC designs can be compromised, perhaps even screech to a near halt, if the various ways to incorporate IP blocks don’t change.
The recent introduction by Synopsys of Design Compiler 2010 has validated Oasys's Real Time Designer approach to IC design. When a startup company introduces a new approach to an old problem, the market always wonders whether or not the new solution will have traction among the design community. The absence of competition is a mixed blessing to startups.
Free White Paper
Verification of Multi-Clock Designs This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk
Workshop on
SpyGlass®-CDC
This workshop introduces the clock and reset analysis capabilities in SpyGlass-CDC for use in clock domain crossing (CDC) analysis
Stay tuned to get more out of Atrenta Console user environment in SpyGlass 4.4
Watch your mailbox for registration information on a webinar on how you can leverage the Atrenta Console user environment.
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! www.atrenta.com .
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