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In this Issue
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 Message from Mike Gianfagna
Atrenta enjoyed a very successful show at DAC this year. We were quite busy in our suites for the entire time, and we're glad so many of you could come by and visit us. Please check out our slide show to see if we have captured your smile!
Just before DAC, what started as an ad-hoc effort by Atrenta, Denali and SpringSoft to offer 600 week-long DAC exhibit passes free of charge has evolved into a true I Love DAC fan club where the design automation community can connect and share experiences. DAC is the focal point for our industry. With the vast momentum and innovation that exists within the EDA community, the I Love DAC site provides a place for people to share and reflect on the many experiences that the annual event has on our lives.
I personally urge you to share your favorite DAC story at I Love DAC.
If you missed our comprehensive demos that show how to enter your design, plan the architecture and establish feasibility, and then validate and close your design, please contact your local sales person for an update. Also, please watch for an announcement regarding webinars of these comprehensive demos.
On a lighter note, Atrenta continues to be the home of your EDA idol for the second year in a row - here's a link to the winning performance once again for you to enjoy!
Best regards,
Mike Gianfagna |
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| News and Articles |
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Verification and Generation of Constraints
EDADesignline
Texas Instruments and Atrenta authors highlight and discuss the importance of constraint validation early in the design flow, and analyze the impact of this validation approach on a real design.
Click here to read the article |
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Changing SoC Design Methodologies to Automate IP Integration and Reuse
Design & Reuse
Systems and semiconductor suppliers are increasingly looking at methodology changes that can help accelerate assembly of chips and systems through one or multiple forms of automation. Why?
Click here to read the article |
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RTL Approach Supports Memory BIST and Repair Insertion
Test & Measurement World
Traditionally, you would implement MBIST and repair functionality for SoC designs at the gate level. But now you can use an approach that inserts MBIST and repair at the RTL.
Click here to read the article |
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Atrenta Extends Platform for Chip Architecture Designs
EE Times
Atrenta Inc. has made major extensions to its 1Team-Genesis platform, which supports architectural level chip assembly.
Click here to read the article |
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Verification of Clock Domain Crossing in SoCs : Part Three of Three - Case Study
Chipdesignmag
This SoC was being done for an automobile application, and reliability was of utmost importance considering the direct implication on the risk of loss to human life.
Click here to read the article |
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Verification of Clock Domain Crossing in SoCs: Part Two - SoC Characteristics
Chipdesignmag
There are many characteristics of an SoC design which a CDC verification tool should be able to handle well.
Click here to read the article |
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Verification of Clock Domain Crossing in SoCs: Part One - Tools and Needs
Chipdesignmag
To avoid SoC failures in the field or delays in delivering the SoC (due to late detection of CDC issues), the selection of the right tool for CDC verification is one of the essentials in setting up the right methodology for the SoC design.
Click here to read the article |
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RTL Analysis Is Critical for 45-nm Design Tapeouts
Chipdesignmag
Today's platforms can help designers achieve early design closure and avoid respins.
Click here to read the article |
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Atrenta Collaborates With Sonics and Denali on a 1Team-Genesis Reference Flow to Accelerate SoC Assembly
Design & Reuse
Reference flow aims to create a healthy Eco-System of "Ready to Integrate" IPs through Atrenta SpyLinks™ Program
Click here to read the article |
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Mike Gianfagna Speaks to EDACafe
Click here to view the video |
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Free Whitepaper
Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints Throughout the Design Flow
Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project.
Click here to get your copy |
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Workshop on SpyGlass-Constraints
SoC development involves the validation of constraints at various stages, such as RTL, pre-layout, and post-layout. Resolving constraint inconsistencies between the block and chip levels, between pre-synthesis, pre-layout, and post-layout is highly critical for the timely development of SoC and superior quality of the results. This workshop demonstrates how SpyGlass-Constraints can help achieve this goal of predictive development of your SoC designs.
Click here to register for the workshop
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DAC User Track Presentations
Download these User Track presentations at DAC 2009 detailing customer success stories using Atrenta's advanced technologies:
USER TRACK: Towards Front-End Design Productivity
Assessing Design Feasibility Early with Atrenta's 1Team®-Implement SoC
Speaker: Thierry T. Sejourne - STMicroelectronics, Grenoble, France
USER TRACK: Front-End Power Planning and Analysis
New SoC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs
Speaker: Sarveswara Tammali - Texas Instruments, Inc., Bangalore, India
USER TRACK: Front-End Power Planning and Analysis
Architectural-Level Power Planning and Estimation
Speaker: Francis Maquin - STMicroelectronics, Crolles, France |
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About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! www.atrenta.com . |
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© 2009 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, 1Team and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This message was sent by Atrenta Inc., 2077 Gateway Place, Suite 300, San Jose CA 95110 USA.
Mail to unsubscribe@atrenta.com if you prefer not to receive future e-mail from Atrenta Inc. |
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