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Tips and Tricks: SpyGlass® DFT
Today's designers must worry about the proper hook-up of various IPs during test operations. So how can SpyGlass DFT help in the verification process?
Today's SoCs are multi-million gate designs consisting of multiple IPs which were yesterday's chips, multiple building blocks, memories, MBIST logic, standard test interfaces like TAP controllers, 1500 wrappers and other custom logic. In order to test all of these interfaces, specifically at the RTL, designers need a flexible, generic and extensible test mechanism with high degree of ease-of-use standard.
SpyGlass DFT offers an environment that enables designers to efficiently adopt a test verification system. The verification methodology is assertion based. Designers are responsible for specifying what their verification goals are. The end result of verification is going to be the revelation of one of the following:
i. design spec is correct
ii. initialization sequence application is incorrect
iii. design implementation is incorrect for DFT
Click here for more information on how one of Atrenta's users deployed the SpyGlass DFT-based solution to alleviate complex test concerns. |
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| News and Articles |
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Are Test Engineers More Highly Evolved?
Early Edition Blog - Chip Design
It wasn't long ago that the design community didn't ostensibly care about test. At the front end, RTL designers focused more on clocks, reset connectivity and scannability. Yes, they needed to pay attention to design-for-test guidelines and SoC DFT connectivity, but they were also perfectly happy to throw their design over the wall to the DFT expert. It was the job of the DFT expert to focus on test quality and coverage, at-speed test and ATPG/MBIST. For any problems, the DFT expert would throw it back over the wall to the designer for iterations. Seemingly, the two sides lived in different worlds. |
| Click Here for More |
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Testing One, Two, Three
Chip Design
There are several points where test needs to be considered. Up front at the architectural level is by far the most effective because the less that's done the easier it is to change. But as every design engineer knows all too well, things can go wrong at any moment—and last-minute engineering change orders don't help. |
| Click Here for More |
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RTL Approach to Memory Built-in Self Test and Repair Insertion
Chip Design
This article describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier's qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation – all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation. |
| Click Here for More |
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| Atrenta at ITC |
| Interested in Achieving 99% Test Coverage Early at RTL? Visit Atrenta at ITC to Learn How |
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When:
September 20-22, 2011
Where:
Booth #210, Disneyland Hotel
Anaheim, USA
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| Click Here for Event Details |
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| An Atrenta Seminar |
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Register today for one of Atrenta's upcoming events, and learn how Atrenta's
advanced methodologies and solutions
for SoC analysis and assembly can help
you Fast Track your SoC Design to success.
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| DFT Resources |
DFT White Paper: A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion
This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier's qualified ASIC design kit and BIST libraries. |
| Click Here to Get Your Copy |
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Atrenta Workshop: Design for Test Hands-On Workshop
This workshop demonstrates the testability analysis capabilities of SpyGlass DFT to be used in the RTL hand-off process. It explains how the fault-coverage can be enhanced based on the recommendations from SpyGlass DFT. The workshop will review how to make all the flops scannable, all latches transparent and improve testability of the design. |
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| Click Here for More Details |
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About Atrenta |
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Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys™ products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com .
© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass are registered trademarks , and GenSys is a trademark of Atrenta Inc. All others are the property of their respective holders.
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