In this Issue
 
News and Articles
 
Atrenta SpyGlass®-Constraints SDC Equivalence Verification
Capability Adopted by STARC
EDAcafe
   
Atrenta announces the integration of the SpyGlass®-Constraints SDC equivalence verification capability into the production flow from the Semiconductor Technology Academic Research Center (STARC)
   
Click here to read the article  
 
 
Atrenta's SpyGlass®-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies
EDAcafe
   
Atrenta announced that Fujitsu Kyushu Network Technologies, a leader in innovative technologies for network and service management solutions, has adopted its SpyGlass®-CDC product.
   
Click here to read the article
   
 
More Choices But Less Design Freedom

chipdesignmag
   
"What if” is an indelible part of the lexicon of every SoC architect and design engineer from the front end of the design flow all the way to manufacturing, but while the terminology will persist for years to come the answers and the value of those answers are starting to change.
   
Click here to read the article
   
 
What EDA Needs to Do to Start Growing Again

chipdesignmag
   

Coming from 27 years in the chip industry, I'm struck by the vast difference in perspective between individuals working in the semiconductor and EDA industries. The chip guys take a broad, integrated approach to product development. That's exactly the approach that the EDA industry needs to adopt to start growing again.

   
Click here to read the article
   
 
A Register Transfer Level Approach to Memory Built-in Self Test
and Repair Insertion
chipdesignmag
   
This article describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier's qualified ASIC design kit and BIST libraries.
   
Click here to read the article
   
 
 
     
     
     
  White Paper: Facilitating At-speed Test at RTL

This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.

Click here to get your copy 		 
     
 
 
  Workshop: SpyGlass®-DFT - Design for Test

This workshop demonstrates the testability analysis capabilities of SpyGlass-DFT to be used in the RTL hand-off process, using a combination of design methodology templates and interactive debugging available within SpyGlass. It explains how the fault-coverage can be enhanced based on the recommendations from SpyGlass-DFT. The workshop will review how to make all the flops scannable, all latches transparent and improve testability of the design.

Click here to register
for the workshop
  
     
     
  Webinar: Early Design Closure With SpyGlass
View the recording of the recent Early Design Closure With SpyGlass webinar, detailing how you can use SpyGlass platform for the early design closure at RTL, including overviews of early design analysis for logic designers, design of risk-free clock domain crossings, optimized timing with better timing constraints, design for test at RTL and design for low power at RTL .

Click here to register
for the video
  
     
     
  Event Update  
 
Visit Atrenta at EDSFair
Booth #711
Jan 28-29, 2010
Pacifico Yokohama
Kanagawa, Japan

Hear Atrenta's Bernard Murphy Speak in the Low Power Design Session at:
EDSFair 2010 Special Stage Jan 29, 2010 | 11:50a.m. to 12:50p.m.


Joint Atrenta-Denali Seminar
High Quality Semiconductor IP
Jan 27, 2010 | 12:00pm-1:30pm
Santa Clara, CA (lunch provided)
Register Now!

 
 
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!   www.atrenta.com .

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