• Three Views on Verification Challenges
• An RTL solution to Test Integration Challenges
• Power-Intent Standards Vie for Designers' Loyalties
• Workshop on SpyGlass®-DFT Solution
• Atrenta@DATE 2008
• Atrenta@MUSIC
  

Three Views on Verification Challenges Chip Design Magazine

The objective of functional verification is to ensure that the design operates correctly for all possible functional scenarios. This requires us to define what all of the possible scenarios are. Read More...

Power-Intent Standards Vie for Designers' Loyalties Electronic Design

About three years ago, timing closure for large system-on-a-chip (SoC) designs began to develop into one huge headache. Every EDA vendor’s toolset had its own interpretation of timing constraints, and there was little or no consistency between those representations. Read More...

An RTL Solution to Test Integration Challenges SCDsource

Design-for-test (DFT) often involves the integration of a test controller to control the test modes for testing a complete system-on-chip (SoC) design or the sub-chip components. Test modes are implemented to accommodate different manufacturing test strategies such as stuck-at test, at-speed test, memory built-in self test (BIST) and boundary scan. DFT design verification at the SoC level also involves satisfying the block-level DFT requirements at the chip level. Read More...

This workshop demonstrates the testability analysis capabilities of SpyGlass-DFT to be used in the RTL hand-off process, using a combination of design methodology templates and interactive debugging available within SpyGlass. It explains how the fault-coverage can be enhanced based on the recommendations from SpyGlass-DFT. Click here to register for the training.

Atrenta @ DATE 2008

Visit the Atrenta booth (# F21) at DATE this year to learn more about our brand-new design flow-oriented methodologies and advanced tools for RTL analysis and optimization – all focused on getting it right from the start! Click here for details.

Achieve better timing & faster closure with the Atrenta's SpyGlass-Constraints solution & Magma solutions

Visit Atrenta in the partner fair at MUSIC (Magma Users Summit on Integrated Circuits)
Silicon Valley:
When: February 28, 2008
Where: Santa Clara Convention Center, Santa Clara, CA

Click here for details.