In this Issue

 
News and Articles
 
Mind the Gap
chipdesignmag
   
Throughout system-level design there are gaps. High-level modeling doesn't connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted
   
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Arasan Joins Atrenta's SpyLinks™ Partner Program
EDACafe
   
Arasan Chip Systems, a leading provider of reusable IP cores for electronic design, today announced that Arasan has joined Atrenta's SpyLinks partner program. Arasan will also adopt Atrenta's SpyGlass RTL platform for development and handoff of "SpyGlass Clean" IP.
   
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EDA: Aging or Dying?
EETimes
   
It is unreasonable to believe that the current technology revolution in the consumer market will continue while EDA dies. Let's agree to stop predicting the death of this important business and rather debate how it will mature (and grow).
   
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Head 2 Head - Take the High Road to Power-Optimized RTL vs Power-Optimization Solution Serves Ubiquitous RTL Designer
   
By ShawnMcCloud, Mentor Graphics & Kiran Vittal, Atrenta Inc
Feb 04, 2010
   
Click here to read the article
   

 
EDA pundits confront market projections for 2010
EETimes
   
2010 has just started, and there is no better time to generate estimates and predictions for this year's EDA market. Three EDA industry experts have agreed to share their projections with EE Times .
   
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STARC Collaborates with Atrenta on EDA Tool Quality Management System
EDAcafe
   
The Semiconductor Technology Academic Research Center (STARC) and Atrenta Inc. announced a collaboration to develop an EDA Tool Quality Management System. This system is based on a QA Data Base provided by STARC and expands the ongoing quality monitoring of Atrenta’s SpyGlass® RTL platform.
   
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STARC Adopts Atrenta SpyGlass®-Power for RTL Power Estimation and Verification
EDAcafe
   
Atrenta's SpyGlass-Power solution is now integrated into version 3.5 of the STARCAD-CEL reference flow for RTL estimation and verification. The STARCAD-CEL reference flow is provided by the Semiconductor Technology Academic Research Center (STARC).
   
Click here to read the article
   

 
Atrenta SpyGlass® Solutions for Early Testability and Low Power Design Adopted by NEC Electronics
SoCCentral
   

NEC Electronics Corporation has adopted the SpyGlass-Power solution for RTL power estimation and reduction, as well as the SpyGlass-DFT solution for early testability analysis.

   
Click here to read the article
   

 
Remaking the Design Landscape
chipdesignmag
   
The change under way now is geographically global. It’s moving to a higher and higher level of abstraction, from semiconductor to system to device. And it is as much driven by business as technology. Moreover, taken in total these changes will completely alter the basic fabric of the design community in ways that have never been seen before.
   
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Yet Another 2010 EDA Trends Write Up?
EDACafe Blog by Ed Lee
   
2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.
   
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Mike Gianfagna Speaks on Sign-off Metrics for IP Quality
 
 
 
     
     
     
     
  White Paper: Low Power Design: Approach and Techniques for Power Estimation, Reduction and Verification

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives.

Click here to get your copy
 
     
     
     
 
 
  Workshop: SpyGlass®-Power - Low Power Analysis Hands-On Workshop

This workshop demonstrates the ability to estimate power early at RTL with different what-if analysis scenarios . Workshop will also walk you through several power optimization approaches and explore the challenges of "getting it right". Topics such as: over-looked enables, inefficient clock enables, wasted data path activity, missing circuitry, power & voltage domain definition and managing multiple power intent across the different stages of the design will be discussed. Real design examples will be used to illustrate these challenges.

Click here to register
for the workshop

 
     
 
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!   www.atrenta.com .

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