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In This Issue
- Message from Mike Gianfagna
- Understanding Clock Domain Crossing Issues
- Training on SpyGlass®-CDC Solution
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Message from Mike Gianfagna
 To our customers, partners and friends: I’d like to introduce myself and talk a bit about the future. I joined Atrenta last summer as VP of marketing. Having been associated with EDA and semiconductors since the pre-"Daisy/Mentor/Valid" days, I have witnessed many, many changes. Process geometries have shrunk beyond reasonable expectations, chip complexity has exploded and semiconductors pervade just about every part of our life.
EDA has played a major role in this remarkable process. EDA has also undergone many changes. Design tools have become more sophisticated, new methodologies have emerged and software usability and interoperability have improved (although seemingly never fast enough). Almost all of these changes can be characterized by "complexity drives abstraction". EDA helps manage design complexity. In many cases, complexity has been tamed by moving the design problem to a higher level of abstraction. The shift from circuit to logic simulation is one example; the design revolution triggered by logic synthesis is another.
Facilitating higher levels of design abstraction is a focus for Atrenta. Our products allow designers to repair bugs and optimize designs very early (when abstraction levels are high and iterations are short). In the years ahead, I believe there will be significant focus on early analysis and optimization – at the RTL level and above.
Atrenta's products will help all design projects to optimize early, avoid costly mistakes and get it right. This is what has lead us to our new tag line: "Atrenta, Right from the Start!" In the months ahead, you will hear more from us regarding this vision. A broad, unified product architecture will help realize the vision. So will design flow-oriented packaging and ultra-easy use models.
Best wishes for a prosperous 2008. I hope Atrenta can help you realize your goals.
Mike Gianfagna |
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Understanding Clock Domain Crossing Issues, EDA Design Lines (Dec 2007) |
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SoCs are becoming more complex these days. A lot of functionality is being added to chips and data is frequently transferred from one clock domain to another. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs. Click here for more.
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Training on SpyGlass-CDC Solution |
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This training introduces the clock and reset analysis capabilities in SpyGlass and SpyGlass Design Constraints (sgdc) files for use in clock-reset analysis. Click here to register for the training
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About Atrenta
Atrenta Inc. is the leading provider of early design closure solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools & methodologies to optimize their designs early in the RTL phase for linting, clock domain crossings (CDC), power estimation and reduction, design for test (DFT), constraints generation and validation including timing exceptions, and RTL prototyping. Atrenta optimized RTL delivers up to 30% efficiency gains in the chip integration, implementation & verification phases. Atrenta has over 130 customers, including the world's top 10 semiconductor companies. Atrenta,
Right from the Start! www.atrenta.com.
© 2008 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and 1Team are registered trademarks and Early Design Closure is a trademark of Atrenta Inc. All others are the property of their respective holders.
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