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In this Issue
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| Atrenta News |
Atrenta CTO Dr. Bernard Murphy to Speak at DesignCon 2011
The panel "The same chip killers keep delaying your schedules - What are you doing about it?" will explore how these design closure risks are being mitigated today, and the options that exist for mitigating them more effectively now and in the future.
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Atrenta to Participate in SemiWiki.com Cloud Based Social Media Platform
Atrenta will participate in a worldwide social media platform aimed at facilitating mass communication for electronic design professionals through Web 2.0 technologies.
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Atrenta Named by EDN in Hot 100 Products of 2010
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Atrenta has been recognized by EDN for introducing one of the Hot 100 products for 2010. The EDA category in EDN's Hot 100 product list contained five entries, including Atrenta's SpyGlass®-Physical product, which was announced at the 46 th Design Automation Conference. |
| Read Full Article |
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| Industry News & Articles |
Soft IP Quality – Who Owns it?
chipdesignmag |
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In October 2010, TSMC raised a few eyebrows when it announced the expansion of its IP alliance program to now include qualification of soft IP readiness. Many asked “Why should a foundry care about the readiness of soft IP? Don't customers hand off GDSII to the foundry? What does the quality of soft IP have to do with the layout being LVS and DRC clean?” It begs the question, who really owns soft IP quality? |
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Experts at the Table: IP Integration Hurdles
chipdesignmag |
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Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys' Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation. |
| Part 1 | Part 2 | Part 3 |
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Supply Chain Adjusts to Design at the System Level
chipdesignmag |
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System-level design is impacting the supply chain at many levels. Software suppliers, IP providers, semiconductor companies, system integrators and OEMs are challenged to work ever more closely together and find a new balance of power for who controls what in the content of an SoC. |
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System-Level Technology Conversations Shift to Deployment
chipdesignmag |
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While much has been achieved to define a system-level design flow, more is still needed. Technology goals vary depending on the perspective of tool providers in terms of what needs to be done to realize the promise of a streamlined tool flow from TLM 2.0 down to GDS II. |
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The Evolution of Design Methodology
EETimes |
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The environment in which design methodology lives is also characterized by periods of relative stability punctuated by discontinuous change when the march of process nodes means that insignificant issues are suddenly major problems and when the scale of designs breaks the old methodologies. New approaches abound and, as in nature, the successful ones live on and others fall by the wayside. |
| Part 1 | Part 2
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Verifying at the System Level
chipdesignmag |
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Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being called upon to generate more software, integrate more IP and do more with the same resources. |
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Will IP Use Increase in Forthcoming SoC Design?
EETimes |
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To answer the question, you have to start with what is driving the future of system on chip (SoC) design. Unless we all suddenly decide to stop buying the next cool electronic gadget on the market, and the one after that, consumer electronics will continue to be the biggest consumer of SoCs. The electronic content in our daily life keeps growing, and so does the need to stay connected wherever we happen to be on the planet. This will continue to fuel the growth of consumer electronics and SoC design. |
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Free Resources |
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Atrenta Tips & Tricks |
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Did you know you can use SpyGlass® to manage your design with automatically generated metrics?
SpyGlass can generate for you design quality & design specification metrics, and provides the ability to generate trend reports over the life cycle of the project. The reports are generated from data mining of SpyGlass generated results. There are two different reports that can be generated from SpyGlass:
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Atrenta DashBoard – For each design block in a chip project or across multiple chip projects, the DashBoard captures a) Design objective metrics like power consumption, test coverage, CDC synchronization, constraints coverage , and b) Design quality metrics including fatals, errors, warnings across a broad range of design checks as defined by the user's SpyGlass methodology. There is also the ability to define pass/fail criteria for each design, quality objective, and perform trend analysis over multiple runs. This report is comes in handy for collaboration amongst members of a design team, as well as for management to track progress across multiple chip projects. |
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SpyGlass DataSheet – The DataSheet programmatically captures the key specs of a soft IP block. This includes IOs, clocks trees, reset trees, power consumption, Blackboxes and other useful data that is required when an IP block is being handed off by the supplier or being accepted by a chip team. Often this information must be extracted from manually created documents or getting into the guts of the RTL. SpyGlass DataSheet automatically extracts this information from SpyGlass analysis of the IP thus preventing manual errors and the need to extract design intent from RTL. |
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These reports are available in standard HTML format, and can easily be integrated into a management dashboard for designs and IPs. These reports can be generated in SpyGlass using the –gen_aggregate_report command in batch or using the Tools menu in the Atrenta Console GUI.
For more details please refer to the Atrenta Console User Guide. |
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The Trouble With Semiconductor IP
Click to Watch the Video
Low-Power Engineering asks what the biggest problem is in IP these days and how to fix it.
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Atrenta Early Edition Blog |
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Getting Some Respect
-By Mike Gianfagna
I've ranted about flawed business models and the Original Sin in other posts. That's not the focus here. Instead, I want to pose one simple question: "Why is EDA the only complex business enterprise software product that is expected to work out of the box?" And what does a lack of respect have to do with the question?
Click to Read |
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CES - The Morning After
-By Bernard Murphy
CES 2010 was quite a party, coming off the misery of 2008-2009. Tablets were everywhere, smart phones are racing ahead, the PC is dead. Our industry is reinventing the electronic experience yet again. I saw one forecast of a $1 trillion consumer electronics market within a few years. This is heady stuff. It restores hope not only in the future of electronics but also the possibility that electronics growth may help to power the global economy back to solid growth.
Click to Read |
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About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys™ products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com . |
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© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass are registered trademarks , and GenSys is a trademark of Atrenta Inc. All others are the property of their respective holders.
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