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In this Issue
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Atrenta Hosts 3-D SoC Design Flow Demo
T&MWorld |
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An effective EDA flow for 3-D chip design will become critical for the development and production of
optimized stacked-die chip systems. Atrenta, AutoESL, Qualcomm, and IMEC have been collaborating on
3-D chip design, and they demonstrated what might be called a working prototype front-end 3-D chip design
system June 14 at the Design Automation Conference at Atrenta’s booth. |
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| Click here to read the article |
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Experts at the Table: Nice to Have Vs. Need to Have
chipdesignmag - Low Power Engineering |
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Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric,
executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon;
Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing
and business development at Springsoft. What follows are excerpts of that conversation. |
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| Click here to read the article |
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Judging IP Quality
IC Journal |
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The Atrenta team recently convened a collection of minds to discuss IP quality. And, while everyone
brought a different perspective, there was general agreement around the table on the points made. |
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| Click here to read the article |
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Mike Gianfagna on EDA360
EDACAFE |
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Mike Gianfagna speaks on how EDA360 helped define the 2010 and beyond definition of EDA value and
how it might alter the industry’s direction. |
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| Click here to read the article |
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Constraints Management
Chipdesignmag - System Level Design |
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As the complexity of designs has scaled, the need to provide accurate physical constraints like
timing, area, power and port locations has become increasingly important. Of these, timing constraints
are the most difficult to provide since they depend on many external factors like floor planning, routing
and integration with other blocks. Properly created timing constraints not only reduce the total effort to
achieve timing closure, but also reduce the number of iterations to achieve that goal. |
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| Click here to read the article |
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| Atrenta's SpyGlass®-CDC Solution Reduces Design Risk for Fujitsu Microelectronics Europe |
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| Fujitsu Microelectronics Europe has adopted its SpyGlass® - CDC product. Fujitsu will broadly deploy the tool
to help reduce the design risks associated with its complex system-on-chip (SoC) designs. |
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| Click here to read the article |
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Wicked Rumor, SpyGlass-Physical, ...and Magic!", Mike Gianfagna
Atrenta at DAC |
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Atrenta Tips & Tricks
SpyGlass-Power |
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Do you know how to make power synthesis more efficient with SpyGlass-Power?
SpyGlass-Power can be used to improve downstream power synthesis efficiency!
The PEPWR03 rule can be used to estimate power savings when clock gating is implemented to replace data-muxing
controlled by an enable signal for flip-flops during power synthesis.
The PEPWR03 rule generates a report that has the details of power savings for the complete design reported per gating cell.
The designer can set a threshold value (in watts) to generate commands for downstream power synthesis tools to NOT implement
clock-gating on candidates that have negative power savings or values less than the threshold value.
The PEPWR03 rule generates a Synopsys Power Compiler™ script that contains set_clock_gating_registers commands for
clock-gating candidates that have negative power saving estimate values. The PEPWR03 rule also generates the Cadence Encounter
RTL Compiler script that contains set_attribute commands for clock gating candidates.
For more details please refer to the SpyGlass Power Estimation Rules Reference Guide. |
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Free White Paper
Power Analysis of Clock Gating at RTL
This White Paper discusses a solution for clock gating analysis and implementation at RTL for power reduction. The RTL approach is
important because designers usually verify power only at the gate level and any change to the RTL needs many design iterations to
reduce power. The RTL solution thus saves weeks of effort by fixing potential power issues up-front.
Click here to get your copy |
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Workshop on
SpyGlass®-Power
This training focuses on Power Estimation, Power Reduction and Power Verification aspects of design to ensure extremely power-efficient designs.
Click here to register
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Webcast: High IP Quality Seminar By Atrenta and Denali |
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About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! www.atrenta.com |
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© 2010 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, 1Team, SpyLinks and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This message was sent by Atrenta Inc., 2077 Gateway Place, Suite 300, San Jose CA 95110 USA.
Mail to unsubscribe@atrenta.com if you prefer not to receive future e-mail from Atrenta Inc. |
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