In This Issue

Atrenta Announces Design-for-Test Solution for
Deep Submicron Circuits
EDA Designline

Atrenta announced an addition to its SpyGlass® design analysis platform - SpyGlass-DFT DSM. The new solution is the industry's first tool which will accelerate design turnaround times by identifying timing closure issues caused by at-speed testing - early at the Register Transfer Level (RTL).
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Power Formats: You Can Have It Your Way
Electronic Design

Though they're more similar than different, the Common Power Format and Unified Power Format still diverge in ways that designers should get to know well.
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Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints Throughout the Design Flow

Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project. Click here to get your copy


Workshop on SpyGlass-Constraints

SoC development involves the validation of constraints at various stages, such as RTL, pre-layout, and post-layout. Resolving constraint inconsistencies between the block and chip levels, between pre-synthesis, pre-layout, and post-layout is highly critical for the timely development of SoC and superior quality of the results. This workshop demonstrates how SpyGlass-Constraints can help achieve this goal of predictive development of your SoC designs.

Register for the workshop on :
http://www.atrenta.com/support/workshops/spyglass_constraints-workshop.htm


About Atrenta
Atrenta Inc. is the leading provider of early design closure solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools & methodologies to optimize their designs early in the RTL phase for linting, clock domain crossings (CDC), power estimation and reduction, design for test (DFT), constraints generation and validation including timing exceptions, and RTL prototyping. Atrenta optimized RTL delivers up to 30% efficiency gains in the chip integration, implementation & verification phases. Atrenta has over 140 customers, including the world's top 10 semiconductor companies. Atrenta, Right from the Start! www.atrenta.com .

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