In this Issue
 
News and Articles
 
Experts at the Table: What's Next?
Low Power Design Community
   
Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation.
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What Will Happen With Verification at 22nm?
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Where Does the Value Shift at Future Nodes? Who Makes the Money?
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Considerations for Choosing the Right Low Power Tool
Chipdesignmag
   
Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow.
   
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Atrenta Inc Receives 2009 Best of San Jose Award
Press Release
 

Atrenta Inc has been selected for the 2009 Best of San Jose Award in the Custom Computer Software Analysis category by the U.S. Commerce Association (USCA).

 
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Atrenta Will Exhibit at the International Test Conference 2009 and Participate in the Panel - "Predictive Solutions for Test - The Next DFT Paradigm?"
Press Release
 

Some designers have suggested the traditional approach to implementing test is outdated; instead, predictive solutions are needed to make architectural tradeoffs and predict test outcomes before implementation.  The panel will discuss the feasibility of predictive solutions, what design and test tradeoffs they should consider, and how accurate they should be.

 
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Atrenta Product Update
 
Announcing SpyGlass 4.3.0 Release

Atrenta recently released SpyGlass 4.3.0. This release continues to build on Atrenta's focus to improve the quality and usability of our products. Some of the key features in the release include:

- Improved support of design encryption to analyze designs containing external IPs
- Improved SpyGlass analysis with uniform rule checking on RTL library cells
- Easier setup for multiple analysis using the Atrenta Console user environment
- Less noise and more accurate CDC analysis with the new and improved rules
- Easy-to-use SDC equivalence with setup guidance and mapping file generation
- Improved testability analysis with the new DFT checks for clock gating
- Further power reduction with the improved SpyGlass-Power reduction flow with auto-fix
 
 
     
     
     
  Free Whitepaper
Verification of Multi-Clock Designs

This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk

Click here to get your copy 		 
     
 
 
  Workshop on SpyGlass®-CDC

This workshop introduces the clock and reset analysis capabilities in SpyGlass-CDC for use in clock domain crossing (CDC) analysis

Click here to register for the workshop
  
     
     
  SpyGlass® 4.3.0 Webinar

Watch your mailbox for registration information regarding the SpyGlass 4.3.0 product webinar.
  
 
About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!   www.atrenta.com .

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