SpyGlass-Power Training

This training focuses on Power Estimation, Power Reduction and Power Verification to ensure power-efficient designs.

Power Estimation at RTL determines where power is consumed in the design while there is still time to make big changes.

Power Reduction through various techniques such as clock gating and activity management open an easier means to low-power design.

Although, the ideas of using multiple power domains or shutting down idle portions of the design are simple, they are immensely powerful as well. SpyGlass - Power utilizes these ideas and several such practices to embed power efficiency in the design process itself, thereby ensuring low power, by design.

Finally, Power Verification eliminates iteration which may come from using a collection of sophisticated power techniques and tools. Trust, but verify.

SpyGlass-Constraints Training

SoC development involves the validation of constraints at various stages, such as RTL, Pre-Layout, and Post-Layout. Resolving constraint inconsistencies between the block and chip levels, between Pre-Synthesis, Pre-Layout, and Post-Layout is highly critical for the timely development of SoC and superior quality of the results. This training demonstrates how SpyGlass-Constraints can help achieve this goal of predictive development of your SoC designs.

SpyGlass Structural and Functional CDC Training

This training introduces the clock and reset analysis capabilities in SpyGlass and SpyGlass Design Constraints (sgdc) files for use in clock-reset analysis. The training covers the following topics:

• The analysis of Clock Domain Crossings (CDC) using standard synchronization schemes, such as 2-Flop, Common Mux Enable
• The analysis of common issues in the design, such as potential race conditions and clock glitches
• How to visualize Clock and Reset Trees in the design
• How to debug the design using parameters in SpyGlass

SpyGlass DFT Training

This training demonstrates the testability analysis capabilities of SpyGlass-DFT to be used in the RTL hand-off process, using a combination of design methodology templates and interactive debugging available within SpyGlass. It explains how the fault-coverage can be enhanced based on the recommendations from SpyGlass-DFT.

General SpyGlass Training

This training course introduces users to the predictive Analysis capability of SpyGlass. The use of SpyGlass in the various methodologies in the RTL Handoff process such as Audit, Block-Design and RTL-Handover are explained in this course.