Academic Qualification
B.E / B.Tech/ M. Tech. in Computer Science/ Electrical/ Electronics Engineering/Math from reputed Universities, preferably IITs

Experience
Minimum 6 to 8 years of relevant experience

Position Responsibilities
The primary responsibilities include RTL to GDSII flow validation from an ASIC design perspective. This would involve developing RTL (Verilog/VHDL/Mixed-HDL) and constraints (SDC, DEF) to validate key transforms, and testing the flow on existing design variants. The candidate would also be required to interface with prospective/current customers to provide on-site support during evaluation and post-sales cycles.

Skills Required
• Very strong knowledge of complete RTL to GDSII flow. Hands on experience of one or more of the reference ASIC Implementation flows is a must.
• Hands on experience of industry standard tools in the domains of Logic/ Physical Synthesis, STA, Timing Optimization, Floorplanning, Place and Route.
• Understanding of nanometer design challenges.
• Proficiency in writing and understanding Verilog, VHDL and Mixed language designs.
• Working knowledge of Scripting languages such as Python, Tcl, Scheme etc. will be a plus.
• Resourcefulness and effective business communication skills.
• Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment.

Reference Code
CAE