His research areas are: computer-aided design of VLSI circuits, computer-aided instruction, real-time systems, combinatorial optimization, and discrete mathematics. He has published over 180 technical papers, and 8 technical books. In addition, he has published three books which are essay collections.
He serves on the Boards of a number of high tech companies and educational and charitable foundations in Taiwan, Hong Kong, and the US. Since 2005, he hosts a weekly radio show on Technology and Humanities in the radio stations IC975 in Hsinchu, Bravo in Taipei, and Mradio in Taichung.
He is a member of Academia Sinica, and a Fellow of IEEE and ACM.
He has authored over 400 technical papers, and 9 books,
Dr. Brayton held the Edgar L. and Harold H. Buttner Endowed Chair in Electrical Engineering at Berkeley from 1996-1999. He is a member of the National Academy of Engineering, and a Fellow of the IEEE and the AAAS. He received the 1991 IEEE CAS Technical Achievement Award, and five best paper awards, including the 1971 IEEE Guilleman-Cauer award, and the 1987 ISCAS Darlington award. He was the editor of the Journal on Formal Methods in Systems Design from 1992-1996. He received the CAS Golden Jubilee Medal and the IEEE Millennium Medal in 2000.
Past contributions have been in analysis of nonlinear networks, electrical simulation and optimization of circuits, and asynchronous synthesis. Current research involves combinational and sequential logic synthesis for area/performance/testability, formal design verification and logical/physical synthesis for DSM designs.
This work spans mixed signal design at the sensor and actuator interfaces to multi-threaded digital system design in the digital processing parts. By using multi-threading and other architectural tricks, substantial power reduction and performance improvement is possible when compared to commodity DSP processors for this problem. A related issue in this domain is fault tolerance in the controller as such controllers are often deployed in nasty environments such as automobiles or space applications. He also works on formal techniques for design representation and related software tools as well as generic chip feasibility and design analysis which are done on a consulting basis.
An example of the formal work is the processor designs above, which are specified in TDL, a very high level language which provides latency tolerance as well as eliminating a large number of critical paths in the resulting core.
He was a co-recipient of several awards including the 1993 IEEE Communications Society's Best Tutorial Paper Award, the IEEE Electron Devices Society's 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the1999 DAC Student Design Contest Award, the first place in the 2004 DAC/ISSCC Student Design Contest Award (operational category), and the ISSCC 2007 Beatrice Winner Award for Editorial Excellence. He held the Analog Devices Career Development Chair from 1994 to 1997. He received the NSF Career Development award in 1995, the IBM Faculty Development award in 1995 and the National Semiconductor Faculty Development award in 1996 and 1997.
His research interests include micro-power digital and mixed-signal integrated circuit design, wireless microsensor system design, ultra-wideband radios, and emerging technologies. He is a co-author of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005).
He has served as a technical program co-chair for the 1997 International Symposium on Low Power Electronics and Design (ISLPED), VLSI Design '98, and the 1998 IEEE Workshop on Signal Processing Systems. He was the Signal Processing Sub-committee Chair for ISSCC 1999-2001, the Program Vice-Chair for ISSCC 2002, the Program Chair for ISSCC 2003, and the Technology Directions Sub-committee Chair for ISSCC 2004-2007. He is the Technology Directions Chair for ISSCC 2008. He was an Associate Editor for the IEEE Journal of Solid-State Circuits from 1998 to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meetings committee chair from 2004 to 2007. He is a Fellow of the IEEE. He is the Director of the MIT Microsystems Technology Labs.
His primary research interests are in Computer Vision, Processor and SoC Architectures and he leads the Reconfigurable Digital Systems Research Group at the University of Moratuwa which work in the area of hardware acceleration, novel architectures for application specific processors and SoCs to improve performance and power efficiency. Since 2004, he has been focusing heavily on reconfigurable logic systems and their applications in Computer Vision, Mobile Communications, Networking and Biomedical Signal Processing.
For more information, please visit Ajith's web page: http://www.ent.mrt.ac.lk/~pasqual
Dr. Cong's research interests include computer-aided design of VLSI circuits and systems, design and synthesis of system-on-a-chip, programmable systems, novel computer architectures, nano-systems, and highly scalable algorithms. He has published over 280 research papers and led over 30 research projects supported by DARPA, NSF, SRC, and a number of industrial sponsors in these areas. He served on the technical program committees and executive committees of many conferences, such as ASPDAC, DAC, FPGA, ICCAD, ISCAS, ISPD, and ISLEPD, and several editorial boards, including the ACM Trans. on Design Automation of Electronic Systems and the IEEE Trans. on VLSI Systems. Dr. Cong served on the ACM SIGDA Advisory Board in 1993-99, the Board of Governors of the IEEE Circuits and Systems Society 2000-04, and been a guest professor at Peking University since 2000.
Dr. Cong received a number of awards and recognitions, include the Best Graduate Award from Peking University in 1985, and the Ross J. Martin Award for Excellence in Research from the University of Illinois at Urbana-Champaign in 1989, the NSF Young Investigator Award in 1993, the Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, the ACM/SIGDA Meritorious Service Award in 1998, and the SRC Technical Excellence Award in 2000. He also received three best paper awards including the 1995 IEEE Trans. on CAD Best Paper Award, the 2005 International Symposium on Physical Design Best Paper Award, the 2005 ACM Transaction on Design Automation of Electronic Systems Best Paper Award, and the 2008 International Symposium on High Performance Computer Architecture (HPCA), respectively. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008.
Prof. Kahng has published well over 300 journal and conference papers. His Ph.D. graduates (Robins, Hagen, Boese, Alpert, Tsao, Muddu, Huang, Markov, Liu, Chen, Mantik, Xu, Wang, Reda, Gupta) have gone on to notable successes in both academia and industry. He has received NSF Research Initiation and Young Investigator awards, 11 Best Paper nominations, and 6 Best Paper awards (DAC, ISQED (2), ICCD, ASP-DAC/VLSI Design, and BACUS). He was the founding General Chair of the 1997 ACM/IEEE International Symposium on Physical Design, co-founder of the ACM Workshop on System-Level Interconnect Prediction, and defined the physical design roadmap as a member of the Design Tools and Test technology working group (TWG) for the 1997, 1998 and 1999 renewals of the International Technology
Roadmap for Semiconductors (International Technology Roadmap for Semiconductors). He has also served as a member of the EDA Council's EDA 200X task force, which produced this report. He has been Chair of the U.S. Design Technology Working Group, and of the Design International Technology Working Group, for the 2001 renewal, 2002 update, and 2003 renewal of the International Technology Roadmap for Semiconductors.
He was Technical Program Chair of EDP-2001 (the workshop of the Electronic Design Processes Subcommittee of the IEEE DATC), and General Chair of EDP-2002. He was also on the steering committees of ISPD-2001/2002 and SLIP-2001. He is currently the Technical Program Co-Chair of the 2004 Design Automation Conference, and remains on the committees of ISPD, SLIP, and EDP, as well as on the editorial boards of IEEE Transactions on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and Test (where he contributes the regular column, "The Road Ahead").
Prof. Kahng's research interests include the VLSI design-manufacturing interface, VLSI physical layout design and performance analysis, combinatorial and graph algorithms, stochastic global optimization, and (as the opportunity arises) other areas of applied algorithmics such as bioinformatics or computational commerce.
For more information, please visit Alan's webpage:
Dr. Pedram has served on the technical program committee of a number of conferences and workshops, including Design Automation Conference (DAC), Design and Test in Europe (DATE), Asia-Pacific Design Automation Conference (ASP-DAC), International Conference on Computer Aided Design (ICCAD), International Symposium on Low Power Electronics and Design (ISLPED), International Symposium on Physical Design (ISPD), and International Workshop on Logic Synthesis (IWLS). Dr. Pedram was a co-founder and general chair of the 1995 International Symposium on Low Power Design and the technical co-chair and general co-chair of the 1996 and 1997 International Symposium on Low Power Electronics and Design, respectively.
He was the Technical Chair of the 2002 International Symposium on Physical Design and is the General Chair of the 2003 symposium. Dr. Pedram has given several tutorials on low power design at major CAD conferences and forums including, DAC, ICCAD, and ASP-DAC. He has published more than 300 journal and conference papers and written four books on various aspects of low power design.
Dr. Pedram is an IEEE Fellow and an ACM member. He serves on the Advisory Board of the ACM Special Interest Group on Design Automation. He served as an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and ACM Transcations on Design Automation of Electronic Systems. He received the 2000 Distinguished Service Award of ACM - SIGDA for contributions in developing the SIGDA Multimedia Monograph Series and organizing the Young Student Support Program. Dr. Pedram was a member of the Board of Governors of the IEEE Circuits and Systems Society from 2000 to 2002, Chair of the Distinguished Lecturer Program of the IEEE CASS for 2003 and 2004, and the CASS VP of Publications in 2005 and 2006.
He was an Assistant Professor in the Department of Electrical and Computer Engineering at Iowa State University from 1992 to 1997. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits, and are primarily centered around physical design, timing and simulation issues, and optimization algorithms. He has authored/coauthored/coedited five books and has served on the editorial boards of the IEEE Transactions on VLSI Systems (current) and the IEEE Transactions on CAD (currently as deputy editor-in-chief)
and the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (in the past), has served on the Technical Program Committee for various conferences, including as technical program co-chair for DAC 2006 and 2007. He has been a Distinguished Visitor for the IEEE Computer Society and a Distinguished Lecturer for the IEEE Circuits and Systems Society, and is a recipient of the NSF Career Award, the SRC Technical Excellence Award, and best paper awards at the DAC'97, ICCD'98, DAC'01 and DAC'03 conferences. He is a Fellow of the IEEE.
For more information, please visit Prof. Fabio's webpage:
She has been an Organizing Committee member of Design Automation and test in Europe, IEEE VLSI Test Symposium, IEEE On-Line Test Symposium. She was General Chair of IEEE On-Line Test Symposium in 2005, and Program Chair of DCIS Conference in 2008 and 2009, SERESSA from 2006 to 2008. She was the University Booth chair of DATE 2011. She is the Friday Workshop Chair for DATE 2012 and 2013 and General Chair of European Test Symposium 2012. She has been involved in European FP and Eureka Projects, as well as French national projects. Dr. Anghel has been recipient of several Best Paper Awards, including one in DATE and IEEE VTS conference.
The research activities of Bernd Becker have been primarily in the area of computer-aided design, test and verification of (digital) circuits and systems. More recently, he has been working on verification methods for embedded systems and test techniques for nano-electronic circuitry. He has published more than 300 papers in peer-reviewed conferences and journals and has been on the programme committees
of numerous major international conferences.
He is a Co-Speaker of the DFG Transregional Collaborative Research Center "Automatic Analysis and Verification of Complex Systems (AVACS)" and a Director of the Centre for Security and Society, University of Freiburg. He is a fellow of IEEE and Member of Academia Europaea.
For more information, please visit Professor Becker’s web page: http://www.informatik.uni-freiburg.de/~becker
His main research areas are in the development and design of data structures and algorithms with a focus on circuit and system design. Dr. Drechsler published over 150 scientific papers and more than 10 books in the areas of testing, verification, synthesis and reasoning technology.
He was member of the program committees of numerous international conferences (e.g. DATE, DAC, ICCAD, VLSI Design, ASP-DAC, VLSI-SOC, EUROMICRO, FDL, FMCAD, CHARME, GECCO, EMO) and served as topic chair for formal verification for the Design, Automation and Test in Europe (DATE) and the Design Automation Conference (DAC).
Wolfgang Kunz conducts research in the area of System-on-Chip design and verification. Past contributions include algorithms for automatic test pattern generation (ATPG), combinational and sequential equivalence checking, logic synthesis, synthesis for test and layout-driven synthesis. His current research is focused on property checking for hardware and low-level software, SMT-solving based on computer algebra and techniques for system-level modeling.
For his research contributions Wolfgang Kunz has received several awards including the Berlin Brandenburg Academy of Science Award, IEEE Trans. on CAD Best Paper Award and the Award of the German IT Society. Wolfgang Kunz is a Fellow of the IEEE.
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