Early Design Analysis for Logic Designers
Using many advanced algorithms and analysis techniques, SpyGlass provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
SpyGlass provides detailed information about many aspects of the design, including syntactic correctness, power consumption, testability, constraints definition, clock synchronization and routability. SpyGlass delivers this broad insight by utilizing many advanced analysis techniques.
What’s Under the Hood
SpyGlass contains a wide array of chip analysis algorithms.Spanning formal techniques, global placement and routing, synthesis, extraction and a variety of simulation, timing, test and power engines, SpyGlass utilizes this technology to create a hardware virtual prototype of the design. This hardware virtual prototype is then analyzed to provide valuable information about what the design will look like after implementation. The hardware virtual prototype can also be optimized to create a design that meets the power, performance and area requirements of the project early in the design process, at RTL.
Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.