SAN JOSE, Calif. - January 14, 2002 - Atrenta Inc. introduced SpyGlass 3.0, a predictive analysis tool that cuts integrated circuit (IC) design time by providing the industry's first structural analysis of RTL (register transfer level) code. With its built-in fast synthesis engine, SpyGlass 3.0 can detect very complex structural problems at RTL that otherwise only show up at the gate level. SpyGlass 3.0's new graphical user interface (GUI) correlates the RTL coding violations with schematics (automatically generated) to help designers get to the source of the problem and figure out the best way to debug their design. By being able to predict where RTL code will cause problems later in the design cycle, SpyGlass helps eliminate time-consuming design iterations. The designs created are better optimized, reusable, and go through the design flow with minimal problems.

An independent survey by Zeidman Consulting found that by using SpyGlass, designers can achieve a 15-20 percent reduction in the time to get new chips to market and a 10-15 percent reduction in design costs. This survey also found a 6X reduction in ramp-up time for knowledge capture and a 60 percent reduction in compliance checking for design reuse.

"Spyglass has been successfully employed as the standard qualification tool for Motorola's RTL reuse coding rules," noted Dr. Wolfgang Eisenmann, Engineering Manager, Architecture and Systems Platforms Group of Motorola's Semiconductor Products Sector. "By having the reuse rules automatically checked, SpyGlass saves us months of laborious manual checking on every new project. We are now further expanding the Spyglass application into other domains," Dr. Eisenmann added.

"SpyGlass 3.0 takes RTL analysis to a new level by being able to find the really hard structural problems for our customers, " stated Atrenta Chairman, CEO and President Dr. Ajoy Bose. "By catching errors early, SpyGlass greatly reduces the number of design iterations and optimizes the RTL for downstream tools."

"At Agilent, we have defined a number of guidelines for RTL design and have found SpyGlass to be invaluable in helping designers meet these guidelines early in the design cycle," said Rob Aitken, R&D Section Manager at Agilent's Imaging Electronics Division. "We are able to program our guidelines in SpyGlass and have it check the RTL for compliance. Having a built-in synthesis engine allows us to check for problems that are difficult to detect with just RTL analysis and this avoids costly synthesis re-runs," Aitken added.

Structural Analysis Predicts Down-Stream Problems
SpyGlass 3.0 uses predictive analysis to look at the structure of the design, finding down-stream problems that are not detectable by other methods including other rule checkers, simulators and formal verifiers. Atrenta has developed a unique technology that uses fast synthesis to create a gate-level representation so true structural analysis can be performed during the RTL design phase. New checks include tests that can predict problems with complex clock synchronization, tri-state bus decoders, combinational loops, logic cone depth, and read-before-write in sequential circuits.

Fast Synthesis - the Key to Predictive Analysis
SpyGlass employs a proprietary fast synthesis engine that can synthesize a large, 3-million-gate design in less than 30 minutes. Synthesis allows SpyGlass to look at the hierarchy in the design, checking for issues with inferred objects, such as inferred latches, flip flops, muxes, and counters. Then SpyGlass takes the hierarchical gate-level structure and flattens it, looking for complex problems such as combinational loops, decoding errors, multi-clock domains and complex synchronization problems that often aren't even found in simulation.

One of the biggest benefits of SpyGlass' ability to delve deep into the structure of the design is that it can do in-depth tests. "If the design is very complex with parameters, complex loops and multiple levels of hierarchy, simple rule checkers are easily fooled into generating false error reports," stated Dr. Bernard Murphy, Atrenta's Vice President of Product Development. "SpyGlass's built-in synthesis engine allows us to accurately expose the underlying design structure and thus eliminate the primary causes of false errors."

New GUI Speeds Debug SpyGlass
3.0's new GUI can display a schematic of the synthesized logic so designers can cross-probe between their RTL code and the schematic. Since the software is completely contained within the SpyGlass package, accurate pointers are maintained from both the synthesis level and the flat level back to the source RTL. Violations are highlighted on the schematic along with the corresponding RTL code. Designers can cross-probe between RTL and schematic views to get a good understanding of the problem and how it might best be fixed

Advance Analysis Eliminates Wasted Real Estate
Because conventional synthesis does not, by default, share resources, often silicon real estate is wasted. If overlooked, increased die size and power requirements are noticed when it is much too late to change the design. By evaluating the RTL code at a structural level, SpyGlass can find places where resources can be shared thereby optimizing area and power consumption.

Additionally, because SpyGlass includes a fast synthesis engine, it can provide designers with an early rough gate count for their design. This lets designers do trade-off analysis early in the design cycle and experiment with the gate-count-costs involved in different design techniques. SpyGlass can give gate-count and logic depth information down to the module level, so designers can pinpoint areas that are consuming the most real estate and, potentially, cause timing problems and higher power consumption.

New Customization Capabilities
SpyGlass 3.0 provides new customization analysis so the designer can add rules, enable and disable tests, and establish profiles that store a designer's selection of policies, rules and parameters. Designers can choose among various policy decks and rule sets that are organized by functional requirements, such as area, timing, and clocks, and by application selection, such as best practices, RTL handover, synchronous design, and by rules for specific vendors' tools. Designers can use either the PERL or C programming languages for this customization.

Availability
SpyGlass 3.0 is available now. SpyGlass runs on Sun/Solaris 2.5 - 2.8, HP-UX 10.2 and RedHat Linux 6.2 and above. SpyGlass supports VHDL and Verilog, and includes a new rule set for Verilog 2000. It is compatible with industry-wide design tools and environments, assuring that it can be used seamlessly within a customer's current design flow.

About Atrenta
Atrenta offers a new approach in accelerating the design of complex ASICs and SoCs through predictive analysis. Its SpyGlass is the first tool that performs detailed structural analysis on register-transfer-level Verilog and VHDL code in order to check for complex problems, which include coding styles, RTL-handoff, design re-use, clock/reset requirements, and much more. Its breakthrough and innovative "look-ahead" capability incorporates a fast-synthesis engine, cycle-based simulation, and testability technologies. Atrenta has over forty customers, such as Agere, Agilent, Apple, ARM, Canon, Compaq, Fujitsu, Hitachi, LSI Logic, Motorola, National Semiconductor, NCR, Nortel and Olympus, who are using SpyGlass to achieve shorter overall design cycles, increased design productivity and lower costs.

Atrenta is headquartered in San Jose, California, with European headquarters in Swindon, England, a research and development center in India, and a sales and support distributor in Japan. For further information, visit the Atrenta website at www.atrenta.com or call 1-866 ATRENTA.

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For further information, please contact:

Mona Singh
Marketing Communications Manager
Atrenta Inc
408-467-4248
mona@atrenta.com

Sherrie Gutierrez
Account Manager
MCA Public Relations
650-968-8900 x 127
sgutierrez@mcapr.com