Company speaks out on business & technical issues affecting design quality

What:
Session 3-WA2 Technical Paper
A Spreadsheet-Based Executable Specification for Scalable Multi-Million Gate SOC Design

Session BF-W2 Business Forum Panel
Total IP Solutions Required to Ease SoC Integration

Session TP-W1 Technical Panel
Getting to Design Quality Closure Without Compromising Productivity

Who:
Session 3-WA2:
Martin Baynes, Product Director, 1Team®-Genesis, Atrenta (Presenter) Anshuman Nayak, Senior Manager, 1Team-Genesis, Atrenta (Author) Bernard Murphy, CTO, Atrenta (Author) Sanjay Churiwala, Senior Director, Atrenta (Author) Chirag Gupta, Texas Instruments (Author) Paresh Joshi, Texas Instruments (Author)
Session BF-W2:
Satish Soman, Chief Solutions Architect, Atrenta (Panelist)
Session TP-W1:
Piyush Sancheti, Senior Director, Business Development, Atrenta (Panelist)

When:
Session 3-WA2: Wednesday, February 3, 9:20 am - 10:00 am
Session BF-W2: Wednesday, February 3, 10:10 am - 11:40 am
Session TP-W1: Wednesday, February 3, 3:45 pm - 5:00 pm

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world\'s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!

For more information, contact:

Corporate:
Charu Puri, Corporate Marketing
Tel: +1-408-493-3514
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Tel: +1-650-363-0142