San Jose, Calif. - May 25, 2010 - Atrenta Inc. today announced that they will conduct live demonstrations of a working 3D design flow at the upcoming Design Automation Conference in Anaheim, California on June 14 - 16, 2010. The live demonstrations will be conducted in the Atrenta booth (#744) and the AutoESL booth (#1577).

3D stacked die manufacturing technology holds the promise of integrating different semiconductor technologies into one high performance package, allowing the design of highly optimized systems at reduced cost and improved performance. In order to realize the benefits of this emerging technology, design methodology and the associated electronic design automation (EDA) tools will need to be enhanced and extended to address the unique challenges associated with multi-technology system design. The design flow that will be demonstrated at DAC is an early version of a working system that addresses 3D-aware high-level synthesis, early partitioning, floorplanning and multi-domain analysis. The system is the result of on-going collaboration between Atrenta, AutoESL and Qualcomm Incorporated.

"Early partitioning, floorplanning and analysis yields substantial benefits for design predictability on conventional advanced SoCs," said Ravi Varadarajan, Atrenta Fellow. "With the emergence of 3D multi-technology design, this activity now becomes an absolute must-have.  You simply cannot hand off a 3D design to back-end implementation without knowing for certain that it is partitioned correctly."

"High-level synthesis is finally moving into the mainstream, and complexity is driving this change," said Atul Sharan, president and CEO of AutoESL. "The daunting challenges of 3D design demand a 3D-aware high-level synthesis approach."

"Qualcomm has been developing a vision for a design system to address the needs of 3D for several years," said Riko Radojcic, director of engineering for Qualcomm CDMA Technologies. "We are delighted to see our vision, PathFinding, moving closer to reality through this collaboration."

Attendees of the Design Automation Conference may sign up so see the demo by visiting either http://www.atrenta.com/DAC2010/sessions.html or www.autoesl.com/dac.php .

About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world's top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com . Atrenta, Right from the Start!

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Atrenta, the Atrenta logo and Early Design Closure are registered trademarks of Atrenta Inc. Qualcomm is a registered trademark of Qualcomm Incorporated. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.  

For more info, please contact:

Atrenta Corporate:
Charu Puri, Corporate Marketing
Atrenta Inc.
Email: cpuri@atrenta.com
Tel: +1-408- 467-4254

Atrenta PR Agency:
Ed Lee
Lee PR
Email: ed@leepr.com
Tel: +1-650-363-0142