About Atrenta

Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys™ products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company.

Corporate Facts at a Glance

Founded:	June, 2001




Funding:	Privately held




Location:	R&D centers in San Jose, US, Noida, India, Grenoble, France and direct sales & support offices in Silicon Valley, Southern California, Texas, North Carolina, France, Germany, UK, Japan, Taiwan, Israel and India. Distributors in China and Korea.




Employees:	Over 300 worldwide; 75% in research and development


Products:	Atrenta's SpyGlass® and GenSys™ product lines form a complete, proven solution to achieve Early Design Closure. Atrenta tools provide an environment to achieve certification of RTL/Netlist and constraints for predictable implementation. These product families addresses issues with architecture capture, IP import and chip assembly, synthesizability, CDC, power management, constraints management, DFT and area, timing and power estimates. Atrenta's GuideWare™ reference methodologies allow our Early Design Closure solutions to easily fit into your existing design flows. RTL Verification & Optimization- SpyGlass® Product Family SpyGlass - Early design analysis for logic designers SpyGlass CDC - Industry's most comprehensive, practical, and powerful CDC solution SpyGlass DFT - Design for test at RTL SpyGlass Power - Design for low power at RTL SpyGlass Constraints - Specify constraints early, validate continuously & automate handoff SpyGlass Physical- Early implementation readiness analysis for RTL blocks Design Capture & Exploration- GenSys™ Product Family GenSys Assembly - Architecture capture and chip assembly GenSys IO - Manage complex I/O subsystems GenSys Registers- Automated register management Design Methodology Support GuideWare™ - Reference methodologies





Growth:	Seven consecutive years of revenue growth




Customers:	170+




Patents:	17 granted and 5 patents pending