Electronic Design and Solution Fair 2009
Booth #711
Jan 22-23, 2009
Pacifico Yokohama, Japan |
Seminar Details
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| Date & Time | : | Jan. 22 1:00 p.m. -2:15 p.m. |
| Room | : | DM1 |
| Agenda | : | Introduction of Low Power & Power Verification at RTL Design with SpyGlass? -Power |
| Presenter | : | Yasuhiro Omori, Senior Application Engineer, Atrenta |
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| Date & Time | : | Jan. 22 2:30 p.m -3:15 p.m |
| Room | : | DM1 |
| Agenda | : | SDC Equivalence/Timing Exception Verification & Generation with SpyGlass? -Constraints |
| Presenter | : | Osamu Yaegashi, Senior Application Engineer, Atrenta |
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| Date & Time | : | Jan. 22 3:30 p.m -4:15 p.m |
| Room | : | DM1 |
| Agenda | : | Physical Aware RTL Debug Environment by Atrenta's Third-Generation RTL Prototyping - 1Team? -Implement |
| Presenter | : | Yutaka Tanigawa , Field Application Engineering Manager , Atrenta |
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| Date & Time | : | Jan. 23 1:30 p.m -2:15 p.m |
| Room | : | DM6 |
| Agenda | : | The Latest CDC Methodology for SoC Design |
| Presenter | : | Osamu Yaegashi, Senior Application Engineer, Atrenta |
| | | |
| Date & Time | : | Jan. 23 2:30 p.m -3:15 p.m |
| Room | : | DM6 |
| Agenda | : | Introduction of Low Power & Power Verification at RTL Design with SpyGlass? -Power |
| Presenter | : | Yasuhiro Omori, Senior Application Engineer, Atrenta |
| | | |
| Date & Time | : | Jan. 23 3:30 p.m -4:15 p.m |
| Room | : | DM1 |
| Agenda | : | GuideWare ? An Effective Methodology to Utilize SpyGlass? Tool Suite |
| Presenter | : | Kenichi Komiya , Senior Field Application Engineer , Atrenta |
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| Date & Time | : | Jan. 23 4:30 p.m -5:15 p.m |
| Room | : | DM1 |
| Agenda | : | 1Team? -Genesis Accelerates LSI Integration |
| Presenter | : | Kenichi Komiya , Senior Field Application Engineer , Atrenta |
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