- Analytics-December 2009 - Atrenta SpyGlass®-Constraints SDC Equivalence Verification Capability Adopted by STARC, Atrenta's SpyGlass®-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies, A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion, White Paper: Facilitating At-speed Test at RTL, Workshop: SpyGlass®-DFT - Design for Test, Webinar: Early Design Closure with SpyGlass, Atrenta-Denali Joint Seminar - High Quality Semiconductor IP, Atrenta at EDSF and more...

- Analytics-October 2009 - Experts at the Table: What's Next, Considerations for Choosing the Right Low-Power Tools, Atrenta Inc Receives 2009 Best of San Jose Award , Free White Paper : Verification of Multi-Clock Design, Workshop on SpyGlass®-CDC, Atrenta SpyGlass 4.3.0 Release, Atrenta SpyGlass 4.3.0 Webinar and more...

- Analytics-September 2009 - Message from Mike Gianfagna, Experts at the Table: What's Next, Semiconductor Design and Manufacture Predictability, Atrenta Event Update, Atrenta Product Update, Free White Paper : Approach and Techniques for Power Estimation, Reduction and Verification, Workshop On SpyGlass® Power and more

- Analytics-August 2009 - Message from Mike Gianfagna , Verification and Generation of Constraints, Changing SoC Design Methodologies to Automate IP Integration and Reuse, RTL Approach Supports Memory BIST and Repair Insertion, White Paper: Approach and Techniques for Preserving the Intent of Timing Constraints Throughout the Design Flow, Workshop on SpyGlass-Constraints and more...

- Analytics-April 2009 - Design Quality Enhances Company Survival, Experts at the Table: Platform-Based Design, Performance or Time to Market. What's Your Choice?, Streamlining IP-based Chip Design, Hear about Atrenta’s efforts to improve IP quality, Mike Gianfagna Speaks at DesignCon 2009, SpyGlass® Workshop, Free White Paper: SpyGlass® Application in an FPGA to ASIC Conversion and more...

- Analytics-March 2009 - New Atrenta Support Portal, Announcing SpyGlass 4.2.0 Release, Boosting SoC Design Productivity for the iPhone Generation, Recrafting the Concept of EDA, Chip Design in Recession: A View from an ASIC Consolidator, DS2 Adopts Atrenta SpyGlass® for Advanced ASIC Design, Free White Paper: Automated Assembly and IP Integration Techniques for SoCs and more..

- Analytics-February 2009 - Mike Fazeli Joins Atrenta, Tieto Joins Atrenta's SpyLinks™ Partner Program, Atrenta's SpyGlass®-CDC Solution Boosts IP Integration Efficiency for Atheros, Atrenta Seminars in India a Huge Success, Power Opto and Linting in CatapultC and SpyGlass®, Atrenta Recognized as Top 5 EDA Vendor by Siliconindia, Atrenta CEO Delivered Keynote Address at the 22nd Intl. Conference on VLSI Design and more...