| Prof. Andrew B. Kahng (b. Oct. 1963, San Diego, CA) received the A.B. degree in applied mathematics (physics) from Harvard College, and from June 1983 to June 1986 was affiliated with Burroughs Corporation Micro Components Group in San Diego, where he worked in device physics, circuit simulation, and CAD for VLSI layout. He received the M.S. and Ph.D. degrees in computer science from the University of California at San Diego. He joined the UCLA computer science department as an assistant professor in July 1989, and became associate professor in July 1994 and full professor (at age 34) in July 1998. From April 1996 through September 1997, he was on sabbatical leave and leave of absence from UCLA, as Visiting Scientist at Cadence Design Systems, Inc. He resumed his duties at UCLA in Fall 1997, and from July 1998 to September 2000 served as the computer science department's vice-chair for graduate studies. Effective January 1, 2001 Prof. Kahng joined UCSD as Professor in the CSE and ECE Departments. He served as Associate Chair of the UCSD CSE Department from 2003-2004. In October 2004, Prof. Kahng co-founded Blaze DFM, Inc., a Sunnyvale-based EDA software company that delivers new cost and yield optimizations at the IC design-manufacturing interface. He served as CTO of the company during a two-year leave of absence, until returning to the university in September 2006. Prof. Kahng has published well over 300 journal and conference papers. His Ph.D. graduates (Robins, Hagen, Boese, Alpert, Tsao, Muddu, Huang, Markov, Liu, Chen, Mantik, Xu, Wang, Reda, Gupta) have gone on to notable successes in both academia and industry. He has received NSF Research Initiation and Young Investigator awards, 11 Best Paper nominations, and 6 Best Paper awards (DAC, ISQED (2), ICCD, ASP-DAC/VLSI Design, and BACUS). He was the founding General Chair of the 1997 ACM/IEEE International Symposium on Physical Design, co-founder of the ACM Workshop on System-Level Interconnect Prediction, and defined the physical design roadmap as a member of the Design Tools and Test technology working group (TWG) for the 1997, 1998 and 1999 renewals of the International Technology Roadmap for Semiconductors (International Technology Roadmap for Semiconductors). He has also served as a member of the EDA Council's EDA 200X task force, which produced this report. He has been Chair of the U.S. Design Technology Working Group, and of the Design International Technology Working Group, for the 2001 renewal, 2002 update, and 2003 renewal of the International Technology Roadmap for Semiconductors. He was Technical Program Chair of EDP-2001 (the workshop of the Electronic Design Processes Subcommittee of the IEEE DATC), and General Chair of EDP-2002. He was also on the steering committees of ISPD-2001/2002 and SLIP-2001. He is currently the Technical Program Co-Chair of the 2004 Design Automation Conference, and remains on the committees of ISPD, SLIP, and EDP, as well as on the editorial boards of IEEE Transactions on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and Test (where he contributes the regular column, "The Road Ahead"). Prof. Kahng's research interests include the VLSI design-manufacturing interface, VLSI physical layout design and performance analysis, combinatorial and graph algorithms, stochastic global optimization, and (as the opportunity arises) other areas of applied algorithmics such as bioinformatics or computational commerce. |
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