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Customers Testimonials
"SpyGlass, combined with Constraints and DFT tools, is helping us jumpstart design closure at the RTL phase. SpyGlass-Constraints enabled us to detect and correct critical issues with our design constraints including verification of false and multi-cycle paths. SpyGlass-DFT provided test coverage at the RTL-level and helped address scan and testability issues early in the design cycle... We plan to continue its use into our next-generation SoCs."
Peg Williams
Senior Vice President of R&D
Cray
"RTL prototyping is a priority for us at Micronas as it eliminates significant uncertainty & delays during implementation. 1Team-Implement®, Atrenta's RTL prototyping tool has an intuitive user interface that can help to seamlessly tie the logical, physical and timing domains to the RTL source.
1Team-Implement allows us to explore feasibility at architectural level, make informed trade-offs, find & fix problems at RTL source thereby accelerating physical & timing closure."
Ulrich Hummel
Director CAD/CAE
Micronas GmbH
"Our fruitful relationship with Atrenta started a few years ago to first address our need for timing constraint screening capabilities. We initially viewed correct and optimal constraint files as mandatory for guiding synthesis, static timing analysis and back-end tools in order to develop high-performance ASICs and SoCs. We then extended our relationship to encompass the wide spectrum of RTL analysis capabilities available at Atrenta, including DFT, clock-reset, low power and ST design conventions. We saw particular value in being able to leverage this large set of capabilities within our design community thanks to using it as a single platform. After thorough testing and pilot use, Atrenta's SpyGlass solution is now being deployed throughout our company to improve the productivity of our designers, the quality of their output and the information to design management. We look forward to making Atrenta's technology the backbone of our company's RTL signoff kit."
Philippe Magarshack
Vice-President Central CAD & Design Solutions
Front-End Technology and Manufacturing Group
STMicroelectronics
"Atrenta tools and flows play a tremendous role for verification. Atrenta at both RTL and gate level is efficient to catch errors such as "forgotten isolation cells"."
Philippe Royannez
Texas Instruments
ISSCC 2005
"Atrenta predicts test coverage at the RTL level itself. We found that the coverage predicted is within 0.5% of our final ATPG number. This method provided a huge boost to our efficiency and cut down on useless DC iterations."
Himanshu Bhatnagar
Conexant
Deepchip DAC 2004 Report
"Atrenta's tools and technology represent excellent value by exposing issues upfront at RTL which otherwise will amount to expensive inter-design-task iterations."
Chandra Moturu
Hewlett Packard
Deepchip DAC 2003 Report
"We have been able to find real issues by using Atrenta, which has sped up the debug cycle that precedes the actual physical layout work. Constraints are almost harder to get clean than the netlist. This tool has definitely made our work easier and faster."
Jonathan Levi
Toshiba
Deepchip DAC 2003 Report
"All in all, I think this was the best overall RTL analysis tool that I saw for our particular needs."
Jeff Waite
Chip Express
Deepchip DAC 2003 Report
"These guys (Atrenta) are a breath of fresh air compared to most of the EDA companies out there. As far as the usage of the tool is concerned, I have been pleased with it."
Rick Stanton
Cypress Semiconductor
Deepchip DAC 2003 Report
"Extremely user friendly and lots of meaningful options to turn on and off and produce meaningful reports; Quick responses to reported bugs and issues from AE and R&D and willingness to come on site and help when needed and enhance the tool; Well organized set of policies which contain rules that can be filtered out if user choose to do so; Does a good job of detecting clocks and clock domain crossings."
Mehdi Shahbazi
Broadcom
Deepchip DAC 2003 Report
"Atrenta is an awesome tool."
Nicco Bhabu
Chip Express
Deepchip DAC 2003 Report
"I often have to look at a design after it is "done" and (Atrenta) is a very quick way to get an assessment. A good way to keep the designers "honest".
Dan Talley
Skyworks
Deepchip DAC 2003 Report
"We did some initial tests of one other tool (Synopsys' Leda) before we selected Atrenta, creating a matrix articulating our requirements with relative weightings for each tool. We made the decision to use Atrenta based on that overall score and have never had occasion to look back."
Dave Harris
Cypress Semiconductor
Deepchip DAC 2003 Report
"Defining RTL DFT rules checking as a handoff from RTL to the integration team makes the task for the DFT/integration teams much easier."
Helmut Lang
Motorola
Deepchip DAC 2003 Report
"Atrenta's tools are really helpful when a piece of 3rd party IP is thrown at me and I have no clue as to what the clock domains are and what the hierarchy looks like."
Himanshu Bhatnagar
Conexant
Deepchip DAC 2002 Report
"I really see a need (for Atrenta) as the sign-off seems to move from netlist to RTL. As a front end designer I need a feedback about how my block will run smoothly through the back end."
Raimund Soenning
Philips Semiconductor
Deepchip DAC 2002 Report
"Atrenta can expand your ability to enforce a methodology in your project, or across your company."
Yatin Trivedi
Intrinsix
Deepchip DAC 2001 Report
"Atrenta provides a new level of analysis, making it faster and easier to achieve handoff. Use of Atrenta's solution by our customers reduces our risk and non-recurring engineering charges because it ensures process compliance."
Cindy Genther
Agere Systems
"Without Atrenta, some design rule violations may not have been found until very late in the implementation process which could have resulted in missing the market window completely."
Craig Borden
Mindspeed
"SDC constraint files are critical for expressing design intent for synthesis and static timing analysis. Checking the RTL against the SDC constraints for completeness and consistency early in the design cycle minimizes iterations."
Daren Bledsoe
Agilent
"Atrenta's solution allows us to immediately and efficiently check a wide range of problems before moving into subsequent design phases, where corrections are time consuming and costly. With Atrenta the DFT team now has an automated, less intrusive way to communicate DFT requirements to the design teams and to apply DFT checks early to find bugs that had previously caused schedule delays."
Peggy Nissen
AMD
"By having the reuse rules automatically checked, Atrenta saves us months of laborious manual checking on every new project."
Dr. Wolfgang Eisenmann
Motorola
"Atrenta enables our designers to develop testable designs from the start, checking for testability issues as the design progresses and fixing issues as they occur. With the levels of integration we are pursuing, changing the design for testability at the RTL stage before we have committed to gate-level design saves us time-to-market, and is very cost effective."
Sanjay Adkar
NeoMagic
"Having a built-in synthesis engine allows us to check for problems that are difficult to detect with just RTL analysis and this avoids costly synthesis reruns. With Atrenta's solution, we can jointly define and communicate our requirements early in the design cycle and implement them throughout the entire design flow. "
Rob Aitken
Agilent
"Atrenta enables the design groups worldwide to collaborate on company standards and also gives each design group the capability to collaborate within the group by adding their own practices and requirements. The "look-ahead" capability in Atrenta's solution has enabled our design community to consider design and test issues early in the design cycle which has shortened our time to market."
Michael Maul
National Semiconductor
"After careful and rigorous analysis of all available options, including all existing tools currently in use, we found Atrenta's solutions to be the superior choice because it fully met all our requirements - powerful underlying technology , full support for STARC rules including mixed-language support, ability to easily customize rules using C and Perl and the capability to effectively incorporate and deploy our own design rules."
Seiichi Nishio
Toshiba
"Atrenta's solution has greatly improved our ability to rapidly develop complex products without additional resources, or extending the schedule."
Bob Cantwell
Ceterus Networks
"Atrenta is central to our plans for an efficient re-use methodology."
Maurizio Montefiori
Siemens
"Atrenta's solution saves us significant time and expensive EDA tool license usage on our SoC projects."
Darren Wedgwood
Freescale Semiconductor |
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