Success Stories
DAC User Track Presentations
Download these User Track presentations at DAC detailing customer success stories using Atrenta's advanced technologies:
2010 DAC User Track Presentations
USER TRACK: 32nm IBM ASIC Design for Test Methodology
Dave Lackey,Distinguished Engineer, EDA,IBM
USER TRACK: Clock Domain Crossing verification signoff in a multimillion gate SoC
Ayon Dey, Shailesh Ghotgalkar & Gokulakrishnan Manoharan(TI)
Paras Mal Jain & Namit Gupta(Atrenta)
USER TRACK: An RTL Approach to Memory-BIST Insertion with Proprietary Architectures
Marcello Raimondi, Alberto Carava & Frederic Grandvaux (STMicroelectronics)
USER TRACK: A Methodology for Automatic Generation of Register Bank RTL, Related Verification Environment and Firmware Headers
Saurin Patel, Mukesh Chopra, Bhawna Chopra (STMicroelectronics)
2009 DAC User Track Presentations
USER TRACK: Towards Front-End Design Productivity
Assessing Design Feasibility Early with Atrenta's 1Team®-Implement SoC
Speaker: Thierry T. Sejourne - STMicroelectronics, Grenoble, France
USER TRACK: Front-End Power Planning and Analysis
New SoC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs
Speaker: Sarveswara Tammali - Texas Instruments, Inc., Bangalore, India
USER TRACK: Front-End Power Planning and Analysis
Architectural-Level Power Planning and Estimation
Speaker: Francis Maquin - STMicroelectronics, Crolles, France | 
