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	Chip Express Ensures Highest QoR for Structured ASICs Spyglass Enables RTL Handoff
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Chip Express is a leading manufacturer of late-stage programmable Structured ASICs. The company's innovative, patented technology consolidates wafer manufacture tooling, reduces time-to-market and minimizes the cost of initial production. The company's Structured ASIC technology is widely used in computing peripherals, communications, high-end consumer electronics, industrial control, medical equipment and military/aerospace systems.

The 0.18µm CX5000 product family utilizes the combination of an advanced metal programmable logic fabric and optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time. Two CX5000 product lines are available: the System Slice which provides a maximum of 1.8M usable gates and 2.5M bits of memory, and the Memory Pig which delivers over 4.5Mbits of fast SRAM.

The Challenge
Chip Express' technology and design expertise allows the company to take on the most challenging designs. Working with its customers, Chip Express starts with generic RTL, RTL targeted to FPGA implementations, or legacy ASIC designs. The company's engineers implement the ASIC in the chosen Structured ASIC library and complete physical design and manufacture.

Unfortunately many issues can emerge when working with RTL that was not specifically developed for a particular logic library or Structured ASIC architecture. In order to optimize performance and design fitting, Chip Express ASIC engineers must understand the design without having current design knowledge from their customer. A variety of technical issues arise in the new target technologies areas including: clock domain partitioning; reset strategies; identification and location of black box IP; type and connectivity of inferred memories; and design size estimation.

Traditionally Chip Express Field Engineers have used manual inspection techniques to identify these issues and then develop design migration schedules and calculate costs. But they often found it was difficult to accurately set schedules since manual inspection missed many design issues. The result was Chip Express had to assume the burden of numerous iterations during synthesis, additional customer interaction, and cost overruns.

The Solution
Chip Express selected Atrenta's Spyglass ® Predictive Analyzer to be part of their RTL handoff design flow. The Chip Express methodology group first worked with Spyglass to develop a policy (set of analyses) specific to the Chip Express architecture. The tool was then given to the Field Application Engineering (FAE) team to use on their laptops for their work with customers.

Chip Express FAEs now have a powerful inspection tool that analyzes and evaluates prospective designs and provides a detailed understanding of the design in minutes. The Spyglass Analyzer offers early insight into any issues that may prevent the design from moving smoothly through the implementation phase. This analysis enables designers to address potential problems allowing Chip Express to confidently develop a reliable schedule. After the analysis, a specific rule profile is sent in to the Chip Express design team so they can run an incoming inspection.

"Spyglass is our acceptance gate," says Jeff Waite, Senior Staff Engineer at Chip Express. "It ensures that we can streamline the synthesis phase and define an accurate production schedule."

The Chip Express engineering team has developed a set of templates and methodologies used worldwide by the Chip Express field staff to promote good design standards and enable repeatable processes from design to design. Chip Express has deployed advanced analysis such as clock identification, clock domain analysis and tracing, reset identification and consistency, black box identification, inferred memories, and specific coding styles.

"The fast synthesis engine within Spyglass creates the structure so analysis occurs with pinpoint accuracy," explains Waite. "Without the underlying predictive analysis engines, we could not get this level of detail so quickly or early in the process."

Chip Express also found simulation will not detect blocking and non-blocking statements in the same process which lead to problems during synthesis. "We find that we require much less time to setup for synthesis," adds Waite "because the clock and reset analysis performed by Spyglass helps us all the way through layout."

"Spyglass has enabled Chip Express to bring RTL-handoff to our customers," sums up Doug Bailey, Vice President of Marketing at Chip Express. "Since we have established Spyglass as a key part of our structured ASIC development flow, we can accurately predict manpower requirements and develop a reliable prototype delivery schedule. This makes customers happy and enables us to more efficiently operate our design group."