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| Success Stories | | Mindspeed Builds Custom IP Qualification System | | | |
| Mindspeed Technologies ™ , the Internet infrastructure of Conexant Systems, is at the front lines in the competitive telecommunications market. In order for Mindspeed to continue to excel in this tough market, the company has adopted both stringent ASIC design rules and EDA design tool requirements. These requirements are driven by the need to reduce the time to qualify incoming IP, enhance RTL reuse, and reduce overall engineering design time.
The importance of great design tools and an effective design tool flow is not just driven by Mindspeed's own chip development needs, but more importantly by its customers. Mindspeed's customers require the delivery of reliable products in a timely fashion to ensure that the narrow make or break telecom market windows are not missed. Mindspeed's strategy continues to work. It counts as its customers the leading telecom companies in the market: Alcatel, Cisco, Nokia, Huawei, McData, NEC, Nortel and Siemens.
The Mindspeed Chip Design Problem
For a time division multiplex (TDM) line card chip application, one of the largest chip design projects Mindspeed had undertaken, the company had to tie together hundreds of separate IP design blocks. In the receive section of the time division multiplex block were 99 design sub-blocks that had to be synchronized with the rest of the chip. Furthermore, there were over 119 design sub-blocks that had to be synchronized within the transmit section. To ensure that the time division multiplexing function could be tested at full speed on the ATE, a special proprietary clock domain-crossing technique for clock synchronization had to be created. This imposed a critical requirement on the incoming IP blocks that they conform to Mindspeed's synchronization technique; which in turn meant that all incoming IP needed to be qualified to work according to a set of standard design rules that Mindspeed had developed. These rules consisted of Synchronization Rules, Clock and Reset Rules, Timing Rules, Best Practices and Syntax rules. A specification of these rules was given to Atrenta ® and it was found that a majority of the rules were available in . Atrenta ® implemented the remaining rules in to meet Mindspeed's design requirements.
The Errors Flagged
In order to check out the design rules established, the RTL version of the TDM chip was analyzed by the . Several violations were found in the IP blocks. One of the most critical violations that detected was incorrectly synchronized clock crossings. There were over 482 violations of the synchronous clock crossing rule. According to Craig Borden, the manager of front-end ASIC Design Services at Mindspeed, "it was extremely critical that all of the cross domain synchronization problems be found. If not, overall system reliability would have deteriorated significantly." Figures 1 & 2 depict two specific synchronization schemes which were implemented and checked for with the custom rules. | | | | Another critical violation was found in a state machine. The state machine had no default state on power-up (no initialization state). According to Borden, "if the initialization problem had not been detected, intermittent problems at test would have arisen. Failure to detect the problem early could have either resulted in a minor redesign of the circuit, or worse yet yield would have dropped at the test floor."
In all, reported fifteen classes of information with the externally generated IP. Of the fifteen classes, six were informational so there was no need to make changes, six needed to be fixed and three were questionable. In addition to synchronization issues, these violation types included feedback loops, race conditions, implicitly declared nets, incomplete case statements, unequal length in logical compare statements and others.
It is important to note that all of these violations were detected early at RTL before the design had gone through synthesis phase. This allowed Mindspeed to avoid costly iterations of long synthesis and verification cycles with the remote vendor who was based in a different country. Borden observed that "without , some of the design rule violations may not have been found until very late in the implementation process which could have resulted in missing the market window completely."
A True Win-Win For all Parties
Through the extensive RTL analysis of both the individual IP cores and the entire chip design, Mindspeed overcame a number of hurdles in its design and IP qualification process. The company estimates that at least four weeks of manual checking time was saved by screening the incoming IPs through . was quickly able to identify the IPs that failed to meet Mindspeed's specifications. The success of in screening the incoming IPs has led to the standardization of this tool for all IP validation.
Furthermore, in order to expedite the changes necessary in the IPs to meet Mindspeed's requirements, the company asked the IP vendor to run on its designs. With Atrenta's Spyglass providing instant feedback, the IP vendor was able to quickly make the necessary changes in the RTL to meet Mindspeed's specification. Because is the only tool that allows for such in-depth analysis and design specific rules to be developed according to different semiconductor company's needs, the IP vendor saw the benefit of using Spyglass early on in their designs and also became an Atrenta ® customer. |
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