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| Success Stories - Toshiba |  | ASIC and Foundry Business Unit for System LSI Enhances Customer Experience and IC Quality with Atrenta Predictive Development |
Toshiba America Electronic Components, Inc. (TAEC) has more than 25 years of experience in delivering thousands of custom SoC solutions and microcontroller/microprocessor-based standard products for networking, consumer and computer/peripheral applications. The company is an independent operating company of Toshiba America, Inc. a subsidiary of Toshiba Corporation, one of the world's largest semiconductor companies and a leader in technology products with more than 300 subsidiaries/affiliates worldwide. The company has designed some of the industry's most powerful chips including the core for the EmotionEngine™, a processor jointly developed by Toshiba and Sony Computer Entertainment, Inc. for the Playstation ® entertainment system.
Toshiba is well known for its precision, semiconductor manufacturing and is production proven in 90nm technology with up to 12 layers of metal. Toshiba recently completed construction of its 300 mm wafer fabrication facility at Oita Operations in Kyushu, Japan and has announced co-development of 65 nm and 45 nm process technologies.
To ensure a close working relationship during chip design, Toshiba continues to invest in US Design Centers located in San Jose and San Diego, Calif., Richardson, Texas; Bloomington, Minn. and Wakefield, Mass. Design Center projects range from SoC design and development using pre-qualified intellectual property (IP) blocks to RTL or gate-level netlist handoff. For example, last year Toshiba announced the SoCMosaic™ custom chip soft IP platform approach to designing a quick turn SoC. Using the application-oriented platform, customers can mix and match IP blocks from the Toshiba or customer IP library to build a custom chip in 6 months. Time to market can be significantly reduced by utilizing Toshiba engineering services for middleware development and third-party companies who have worked closely with Toshiba to provide HW/SW co-development and emulation tools tailored to the SoCMosaic custom chip methodology.
Business and Technical Challenges
With the onset of 0.13u silicon process and below, the rise of IC complexity has created new technical and business challenges in the industry. Engineers are dealing with many more clock domains, longer logic paths, tighter timing and increasing testability requirements. Business managers and executives are facing shrinking margins, shorter sales windows and tougher competition, so delivery schedule and product quality are paramount.
"One of our greatest challenges is qualifying customers" designs prior to handoff, stated Jon Levi, San Diego Design Center Manager for TAEC. "Many times there are significant delays to fix problems with the customers" deliverables prior to being able to start the implementation project work." The traditional methods of manual inspection and running through preliminary synthesis and timing analysis were noticeably non-sufficient as problems are still discovered much later in the design cycle. This causes late-stage iterations with the customers and puts delivery schedules at risk.
|  | "Toshiba has extended its value proposition by delivering design services for SoC design and Atrenta's Spyglass, a mission critical technology used in our flow, has already proven to support our goal of improved time to profit," said Richard Tobias, vice president, ASIC and Foundry Business Unit, System LSI Group, Toshiba America Electronic Components, Inc. (TAEC).
"Spyglass has enabled our design centers to proactively work with our customers to handoff designs that can be produced faster and with higher quality. |
| Another significant problem area is the creation of valid timing constraints. Since the amount of logic is so great in many of these ICs, multiple clock domains have been swept into the designs. In addition, most of the ICs have some sort of analog function in them as well. This means the creation of a timing constraint file is no longer trivial. All relations must be covered or the downstream tools (synthesis, static timing analysis, place & route) will do something undesirable such as down sizing cells that were supposed to be left alone. "Getting the constraints right is often a long and painstaking iterative process that has a significant impact on the physical layout of the device," said Levi.
Testability has also become a major concern in smaller process geometries - specifically the need for much higher test coverage these large modern SoCs. With high speed interfaces and analog blocks, innovative solutions are developed to give good coverage with the smallest set of vectors. Test engineering is mainly handled at the gate-level, but the poorer the test coverage at RTL, the bigger the challenge is for the test team.
Enhancing Toshiba's Methodology
TAEC's design centers have chosen Spyglass Predictive Analyzer with DFT to be a critical part of their ASIC and SoC design methodology. Spyglass will ensure that what the customer gives TAEC meets the needs of the Toshiba design system so the design centers can successfully reach a manufacturable IC without significant iterations. Spyglass is also used by the design center engineering team for incoming inspection. "The many policies of Spyglass help guide Toshiba's customers toward a syntactically and structurally correct design that is test ready when we take it over," stated Levi. He went on to say "And with the new timing policy, first order timing issues are removed and the design is accompanied by a consistent set of constraints." The design center further refines the constraints throughout the process, but now the starting point is more complete so it covers the design and does not leave large portions without constraints.
So far, Toshiba has found a wide variety of beneficial analyses that can now be run before the long synthesis step. For example, Spyglass analyzes Verilog and VHDL to detect if there are multiple drivers on a single non-tri-state net. This is critical otherwise the physical device could be damaged during operation and this type of error may not be detected by simulation or timing analysis. |
 | | Another area of great help has been in early DFT compliance checking. For example, all latches, except retiming latches, must be transparent in test mode.
Spyglass will identify retiming latches and then simulate test mode. If any non-retiming latches are not transparent, then a violation is reported.
Test engineering knowledge is a key part of Spyglass so design engineers do not have to be test experts in order to make their RTL more test compliant. A few changes early in the design cycle have extremely positive effects on the whole process. Because Spyglass can also provide the test-coverage percentage at RTL, Toshiba can advise to make changes very early to avoid iterations after synthesis and scan insertion.
"The earlier in the cycle you find an error, the greater the savings. The repair time is geometrical - so early (at RTL) is extremely helpful," stated Levi. "We estimate that some of these problems could have cost weeks or even months before the error was caught and corrected."
Another important area has been in clock domain analysis. More of today's ASICs and SoCs depend on many clock domains and quite often clock domain crossings exist without correct synchronization. This type of problem is not often caught by simulation or synthesis, and may go undetected until post-fabrication. This would be a very costly problem for the customer, so it is imperative to have Spyglass analyze clock domains. "Spyglass finds clock design issues early in the RTL cycle. I do not have to wait until synthesis is completed, so engineering time is saved." stated Levi. | | | | | Figure1: This latch is not transparent in test mode and would require ATPG tools to use sequential techniques to develop tests for many of the faults around or through this latch. | | | | |  | | | Figure2: With a simple change to the RTL, the designer can make this latch "transparent" in test mode. | | |
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Early Benefits Seen
"Probably the biggest benefit will be the setting of the ASIC customer expectations early in the cycle. If you can show the ASIC customer that he has work to do before a handoff is acceptable, its better than taking a handoff and coming back to say the handoff was not acceptable, so a delay will be required to fix it. Predictability of the schedule after handoff is much better. This is good for manufacturing (fab) planning and for the customers internal planning as well." stated Jon Levi, San Diego Design Center Manager for TAEC. "Experience has all ready shown that Spyglass smoothes the delivery of gate-level netlist or RTL to Toshiba thereby improving schedules and the quality of the product," said Roger Mar, Staff Design Engineer, TAEC San Diego. Roger went on to say "Spyglass is an invaluable tool to discover design problem early in the design cycle and it is definitely helping Toshiba make RTL handoff become a reality." |
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