Atrenta Testimonials

"Atrenta's latest release of power and deep submicron test solutions for RTL power estimation, reduction and verification offer the right answer to address today's complex design challenges. The version 5.0 of the STARCAD-CEL Reference Flow includes Atrenta's SpyGlass Power and SpyGlass DFT DSM solutions, enabling our customers to find killer bugs and implement low power design strategies while saving multiple iterations of synthesis and tens of hours of power simulations at the gate level."

Nobuyuki Nishiguchi
Vice President and General Manager, R&D Department-2
STARC

"TSMC places high importance on the quality of deliverables from our IP ecosystem. We have worked closely with Atrenta to refine the process of validating the delivered quality of soft IP from our ecosystem partners. The capability we are now putting into production is expected to provide valuable information regarding soft IP quality for our end customers."

Suk Lee
Director, Design Infrastructure Marketing Division
TSMC

"With verification taking as much as 70% of total design cycle time, we believe that verification at the early stages of design can provide significant improvement in productivity. With SpyGlass AuoVerify, we were able to identify deeper RTL issues using formal technologies which are hard-to-find using basic linting or a simulation based methodology. SpyGlass AutoVerify enables us to check 'RTL activation status,' such as checking dead code, FSM deadlocks, unreachable states, static registers and initialized values of registers."

Yuji Yoshitani
Senior Engineer, Development Dept.II, System Logic Development Center
Fujitsu Kyushu Network Technologies Limited

"The timing and physical closure of our SoCs has always been a big challenge for us. We needed a tool that would partition our SoCs based on our requirements, and provide trade-off analysis and guidance for our implementation tools. The SpyGlass-Physical product was able to achieve just that on 40nm and 32nm SoCs in significantly shorter time than we expected..."

François Rémond
Director of CAD
STMicroelectronics

"Atrenta's SpyGlass CDC product is critical in helping us avoid design iterations and general risks associated with our complex designs. We have been very impressed by the comprehensive solution offered by SpyGlass CDC, which allows us to quickly identify real problems in our clock networks at the earliest possible point in the design flow..."

Raimund Soenning
Manager Hardware Development - Graphics Competence Center
Fujitsu Microelectronics Europe

"Atrenta's SpyGlass platform has been instrumental in helping us reach the stringent quality goals we set for our broad IP portfolio."

Chandan Egbert
Senior Director of Engineering
Arasan

"By using SpyGlass-Power for RTL level analysis and efficient clock gating, we were able to reduce power by up to 40% in our wireless chip."

Akira Denda
Department Manager, Device Platform Development Department 1st SoC Operations Unit
NEC Electronics Corporation

(STMicroelectronics) had been looking for a design environment ... focusing initially on architectural-level power analysis, estimation and management, and subsequently on top-down timing budgeting. We were very happy to discover a clear vision match with Atrenta's [GenSys] product."

Philippe Magarshack
Vice President for Central CAD & Design Solutions
STMicroelectronics

"Our advanced digital television chips require automated assembly and sophisticated I/O support. We are pleased with the results we have seen so far using Atrenta's [GenSys]. We plan to use the product for automated assembly and I/O configuration on our latest designs."

Dr. Kang, Yong-Seok
Principal Engineer of Design Technology Part
LG Electronics

"The use of Atrenta SpyGlass for DS2 product development facilitates early bug detection and enhances the reliability and quality of the final ASIC, allowing us to design the best product for our customers... These products help us to achieve excellent results regarding development time, quality of the final ASIC and overall development cost."

Javier Jimenez
ASIC Design Manager
DS2

"The integration of Atrenta's SpyGlass MBIST solution in our front-end design kit has automated ST's proprietary embedded memory test and repair capabilities at RTL. The solution not only allows early and faster validation at RTL, but also allows timing optimization of the complete RTL with memory BIST where area impact is known early."

Frederic Grandvaux
Memory Test Solutions Manager within Central CAD & Design Solutions
STMicroelectronics

We have three designs in advanced phase of development that rely on inserting memory test with the SpyGlass MBIST solution. This automatic solution becomes necessary in devices having huge proliferation of memory instances, as our applications require improving efficiency/lead time in our DFT design flow."

Angelo Oldani
Design Director for the Communication Infrastructure Division
STMicroelectronics

"The Atrenta SpyGlass CDC product provides detailed clock domain synchronization checking, useful for external IP and IP integration verification. We are pleased to adopt this EDA tool to assist us with product development efficiencies."

Rick Bahr
Vice President of Engineering
Atheros

"Atrenta's SpyGlass enables us to gauge quickly the quality of incoming RTL designs from our customers, reduce risks (e.g. effort and time) and then plan project resources and timelines accordingly. For our complex SoC designs, the clock domain crossing [CDC] capabilities in SpyGlass have proven to be mission critical."

Rudolf Krumenacker
Head of Embedded Systems Design
Tieto