Make your RTL implementation ready with the SpyGlass® platform

SpyGlass-Power provides comprehensive, estimation-driven power reduction and broad power verification - from RTL to post-layout, supporting both UPF and CPF.

This demonstration will take you through activity analysis, power estimation, power reduction guidance (including quantification of power savings) and verification of power and voltage domains.

SpyGlass-Constraints improves timing closure and reduces design iterations with comprehensive support for generation, management and verification of design constraints, including false and multi-cycle paths.

This demonstration will show you how to manage constraints in your design flow starting with the generation of SDC at the block level (RTL stage) to reduce design iterations and improve false path/mutli-cycle path exceptions for faster timing closure.

Some of the most common reasons for silicon re-spins today are synchronization issues due to asynchronous clock domain crossings (CDC). Traditional methods like static timing analysis and simulation do not identify these hard-to-detect bugs easily. SpyGlass-CDC enables you to identify clock domain crossing issues at RTL and ensures that clock synchronization is correct.

This demonstration will show you how Atrenta's comprehensive solution can be used for solving CDC problems at the block and chip level. We will show the solution for structural CDC analysis, which includes validation of synchronizers like multi-flops and reporting reconvergence issues. We will also show how SpyGlass-CDC formally proves the correctness of complex synchronization schemes, including data-hold, Gray-coding, FIFOs and handshakes.

SpyGlass-DFT is the leading solution in the industry that addresses testability in hours during RTL design - instead of days later in the design cycle. The product enables RTL designers to create testable designs without becoming test experts and achieve high coverage (98-99%). Our new at-speed test solution, SpyGlass-DFT DSM, addresses the latest deep submicron challenges for test.

This demonstration will run testability analysis at RTL to identify issues that could result in lower test coverage for stuck-at and at-speed conditions (clocks, resets, latches, lack of control on D-pins for launching transitions, etc.). You will see at-speed rules for timing closure, test coverage estimation for at-speed with audit coverage guidance and learn how to use SDC to improve at-speed coverage accuracy.

Our newest extension to the 1Team family allows chip architects to rapidly import design specifications, assemble IP and create correct-by-construction connectivity for complex SoC designs. This innovative product allows fast and accurate capture of high level design intent and facilitates platform-based design.

This demonstration will show you how to capture design specifications, import semiconductor IP, generate connectivity for the design and create register management descriptions.

1Team-Implement enables RTL designers and IP designers to perform early feasibility analyses of their designs, avoiding expensive and time-consuming iterations with implementation tools. With its unique ability to perform analysis that gives insights into the physical domain and a GUI that allows designers to cross-probe these issues directly to the RTL, this solution enables early identification and resolution of potential congestion and timing issues, by empowering RTL designers to make high-impact trade-offs earlier in the project.

This demonstration will show how a designer can get early insights into potential physical issues through the congestion metrics and timing reports and will also show how these metrics can be used to guide topology and micro-architectural changes that alleviate these potential problems.

Enhance your design flow

Atrenta has assembled ready-to-use reference methodologies for new RTL creation, IP reuse and SoC integration. Our design flows will accelerate your adoption of Atrenta's Early Design Closure solutions while reducing false errors/noise and increasing overall design quality and productivity.

This demonstration will take you through the fundamental philosophies of this new product and show you how our ready-to-use methodologies can easily fit into your design flow. We will show you how to perform comprehensive analysis on new RTL descriptions, facilitate IP reuse and ensure SoC integration is done properly.

In this is presentation by Satish Soman, Chief Solutions Architect at Atrenta, you will learn how Atrenta's pre-packaged methodologies have been designed to address common problems encountered in the early stages of RTL and pre-implementation. Satish has over 20 years of experience as a design engineer and design executive. He has a proven track record of delivering over 18 successful tape-outs across designs in multimedia, networking & computing. Satish's presentation is targeted for design engineers & managers. Hear about Atrenta's pre-packaged methodologies direct from a design expert's perspective.

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