The trends towards convergence in applications on a single SoC and increasing design costs, are driving design teams to explore IP reuse and platform-based design techniques to improve overall design efficiency and ROI.

In this demo, you will see how Atrenta's 1Team-Genesis platform provides a structured SoC assembly methodology that enables IP re-use, IP import, automated connectivity generation, registers management, early power planning and power management, I/O planning and generation, early physical planning and topology generation.

Enter your design, plan the architecture and establish feasibility.

A variety of design risks related to structure, timing, test, clocks and power result in design iterations and, even worse, silicon re-spins. In addition, design re-use and IP integration require guidelines for correctness and consistency.

In this demo, you will see how the SpyGlass® platform provides a single integrated flow for RTL analysis and optimization. You will learn how to address problems associated with structure, timing, test, clocks, area, routing congestion and power, all controlled by a reference methodology aligned with the SoC design process. This guided process brings the benefits of SpyGlass to the average RTL designer with minimal tool knowledge as well as the expert user.

Validate and close your design.

Want to learn more? We have focus sessions to meet your needs. These sessions provide detailed discussions on specific portions of Atrenta's flow as well as several business initiatives.

SpyGlass Platform Focus Sessions

Late discovery of chip limitations (timing, area, power tradeoffs) cause iterations and schedule delays. The SpyGlass-Physical solution provides early visibility into physical characteristics at RTL, enabling designers to make local changes to the code and complete verification before handoff to implementation.

This focus session will explain how Atrenta is extending the SpyGlass platform to provide timing, area, congestion and power feasibility reports for RTL design teams to get early insights into the physical characteristics of their RTL block. With SpyGlass-Physical, RTL design teams can ensure compatibility with SoC-level constraints and handoff to implementation with confidence.

You will never close timing without good constraints. The SpyGlass-Constraints solution takes the risk out of timing closure with comprehensive support for the management and verification of design constraints, including false and multi-cycle paths.

This focus session will give you an overview of how SpyGlass-Constraints addresses SDC creation and management. We will outline the process of creating and verifying SDC constraints using only RTL as a starting point, as well as features to ensure constraint consistency as the design transitions from block to chip and from RTL to netlist. Techniques for verifying existing timing exceptions, and identifying new ones to help with timing closure will also be described.

Are you risking bad silicon? Some of the most common reasons for silicon re-spins today are synchronization issues due to asynchronous clock domain crossings (CDC). Traditional methods like static timing analysis and simulation often do not identify these hard-to-detect bugs. The SpyGlass-CDC solution enables you to identify clock domain crossing issues at RTL and ensure that clock synchronization is correct.

The SpyGlass-Power solution provides comprehensive, estimation-driven power reduction and broad power verification - from RTL to post-layout, supporting both UPF and CPF. Low power-aware design requires the designer's attention from the first architectural decisions all the way through to final layout. The designer needs to explore as many architectural tradeoffs that are feasible, and requires fast, accurate determination of the power at all stages of the design flow. Hence, there becomes a growing need for power verification checks to ensure that power intent is still being met throughout the design flow - from RTL to post-layout.

The SpyGlass-DFT solution is an industry-leading product to address testability in hours during RTL design instead of days later in the design cycle. The solution enables RTL designers to create testable designs without becoming test experts and achieve high coverage (98-99%). Atrenta's at-speed test solution, SpyGlass-DFT DSM, addresses the latest deep submicron challenges for test. Our new memory built-in self test (MBIST) solution, SpyGlass-MBIST, provides insertion automation and validation of vendor independent BIST IPs at RTL.

This focus session will take you through testability analysis at RTL to identify issues that could result in lower test coverage for stuck-at and at-speed conditions. You will see at-speed rules for timing closure, test coverage estimation for transition faults with audit coverage guidance and learn how to insert memory BIST at RTL with your ASIC vendor's qualified BIST libraries.

Atrenta's 1Team-Genesis product line enables a structured SoC assembly methodology that enhances the efficiency of your design flow by enabling a seamless IP reuse and automated SoC integration methodology.

Key technical topics in this focus session include automated connectivity generation, I/O pin-muxing, architecture (integration logic) generators and register management.

Atrenta's 1Team-Genesis product line can help you build an architecture-aware SoC assembly methodology that provides early visibility into power, performance and area (PPA) achievable from a given architecture and also allows for some early PPA tradeoffs.

Key technical topics in this focus session include early power domain planning, architectural power management, early physical partitioning and topology planning.

If you are some one who wants to improve design efficiency, quality and reduce cost, you will not want to miss this focus session. The session will highlight how Atrenta's Early Design Closure solution can be deployed to measure design quality, quantify design risk, automatically generate and track key design metrics, and help manage the SoC development life cycle effectively.

If you are a semiconductor IP supplier or a consumer, this focus session will help you to be more effective with management of your IP supply chain. The session will highlight how Atrenta's Early Design Closure solution can be used to measure and improve the quality of IP from its development to handoff, acceptance, and integration into an SoC.

Power optimization starts the minute a design is conceived. If properly guided, high-level synthesis tools can have a substantial positive impact on the power profile of a chip. In this special partner session, Atrenta has teamed up with Mentor Graphics to demonstrate how their Catapult® C Synthesis tool can work with SpyGlass-Power to create a power optimized design.

This session will show how power trade-offs can be addressed during each stage of the ASIC design process, starting from the initial conceptual C++ algorithm all the way to gates by estimating power in SpyGlass-Power.

Atrenta in User Tracks at DAC

Come to DAC 2009 and  hear customer success stories using Atrenta's advanced technologies:

USER TRACK: Towards Front-End Design Productivity
6.3s Assessing Design Feasibility Early with Atrenta's 1Team®-Implement SoC
Speaker:  Thierry T. Sejourne - STMicroelectronics, Grenoble, France

USER TRACK: Front-End Power Planning and Analysis
9.3s New SoC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs
Speaker:   Sarveswara Tammali - Texas Instruments, Inc., Bangalore, India

USER TRACK: Front-End Power Planning and Analysis
9.5 ALPES: Architectural-Level Power Planning and Estimation
Speaker:   Francis Maquin - STMicroelectronics, Crolles, France