Visit the Atrenta booth (# F21) at DATE this year to learn more about our brand-new design flow-oriented methodologies and advanced tools for RTL analysis and optimization – all focused on getting it right from the start!
Some of the highlights of Atrenta's product demonstrations at DATE:
To book a private meeting at DATE, you can email Charu Puri at cpuri@atrenta.com , or contact your local representative. For free exhibition registration, please click here .
We look forward to meeting with you at DATE 2008.
Sincerely,
Bruno Geldreich
European Sales Director
Atrenta GuideWare™
The Atrenta SpyGlass® tool suite is an industry standard for Early Design Closure® during IC development. SpyGlass tools analyze design intent (RTL, netlist and constraints) as soon as it is available and handoff design assumptions (waivers) to downstream implementation tools. Early design analysis with SpyGlass tools ensures the design is verifiable and implementable right from the start. The SpyGlass tool suite offers a single platform with an exhaustive, proven design rule set and a common cockpit environment.
Atrenta's GuideWare™ solution further enhances the customer benefits by grouping SpyGlass rules into templates aligned with the chip development process and validating them for high impact. The GuideWare solution provides a jumpstart for design groups with GuideWare templates usable out-the-box at various phases of the IC design flow (new RTL, IP reuse and chip integration). The reference GuideWare templates can be configured to quickly map to customer-specific design styles.
This demonstration will show how the GuideWare solution can be used to validate semantic issues during new RTL development. In this example, basic design setup issues and test-related issues are analyzed – at a stage where the RTL is becoming reasonably mature.
SpyGlass®-CDC
With extensive IP reuse and complex clocking structures, some of the most common reasons for silicon re-spin in today's designs are synchronization issues due to asynchronous clock domain crossings (CDC). Traditional methods like static timing analysis and simulation do not identify these hard to detect bugs easily.
The SpyGlass-CDC solution enables you to identify CDC issues at RTL and ensures that clock synchronization is correct. It automatically recognizes and formally verifies the functionality of most complex clock synchronization schemes.
The SpyGlass-CDC demonstration will show you how Atrenta's comprehensive solution can be used for solving CDC problems at the block and chip level. We will show the solution for structural CDC analysis, which includes validation of synchronizers like multi-flops and reporting reconvergence issues. We will also show how the SpyGlass-CDC solution formally proves the correctness of complex synchronization schemes including data-hold, Gray-coding, FIFOs and handshakes.
SpyGlass®-DFT
At deep submicron (90nm and below), the need for test quality, yield improvement and design productivity has become extremely important. This can only be achieved by making the design fully testable for all defect models with the least number of design iterations.
The SpyGlass-DFT solution is the only solution in the market that can ensure you reach your testability goals at RTL. The tool identifies poor test coverage causes for stuck-at and at-speed defect models and helps fix these issues, at the same time providing an accurate estimate of test coverage at RTL with a high correlation to ATPG tools (1-2%).
The SpyGlass-DFT demonstration will show how to make your RTL scannable, make latches transparent, add test points, and validate scan chains; all of these in the context of how test coverage can be improved by making these changes.
1Team®-Implement
The 1Team-Implement solution enables chip architects, IP designers and RTL designers to explore the feasibility of their designs rapidly and accurately. The architectural exploration capabilities enable early prototyping of the design specification and enables chip architects to assess the impact of architectural tradeoffs. The RTL analysis capabilities enable IP designers and RTL designers to rapidly identify, debug and fix potential timing, power, area and congestion issues.
This demonstration will show how to get early performance estimates, explore architectural and micro-architectural changes and automatically generate and evaluate multiple floorplans. At the same time, the demo will also highlight how to quickly debug problems by cross probing from the schematic, timing and physical views directly to the RTL source, thereby pinpointing the source of those problems.
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