Are you certain all the blocks in your chip, including third party IP, are interfaced and synchronized correctly? Are you certain you can achieve the highest test coverage quality (>99%)?
 
Can you confidently manage multiple asynchronous clocks spanning different clock domains and verify them accurately to achieve manufacturing test goals?
 
Lunch Seminar: Catching CDC and DFT Bugs
 
Your chip design is serious business and low test coverage could impact the quality of chips shipped. Undetected clock domain crossing (CDC) bugs can also be lurking chip-killers.

Join us for a lunch seminar: Catching CDC and DFT Bugs

Gain vital insights into just how dangerous these hard-to-find bugs can be. Experts from Atrenta, the leading provider of Early Design Closure solutions, will present informative, in-depth information and case studies detailing several CDC and DFT bugs and how to find them early to ensure that your clock synchronizations are correct and your test quality goals are achieved!
 
Agenda

  Design-for-test challenges
     Stuck-at testing
     At-speed testing
     Customer case studies

  Clock-domain-crossing concerns
     Meta-stability and system behavior
     Data hold and reconvergence
     Real killer bugs

  Early Design Closure® concepts
  Overview of the SpyGlass®-DFT and SpyGlass-CDC solutions
  Lunch
 
When:
January 29, 2009
10:00 A.M. - 1:00 P.M.
When:
February 02, 2009
10:00 A.M. - 1:00 P.M.

Where:

Mosaic Hotels
C - 1
Sector - 18
Noida – 201301
India


Where:

The Grand Ball Room
The Leela Palace Kempinski Bangalore
23 Airport Road
Bangalore - 560 008
India


Click here to Register

Click here to Register
   



Note:
Registration for this event is FREE and lunch is included.


Media Partner  
EDN Asia  


About Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!   www.atrenta.com .

© 2009 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, 1Team, SpyLinks and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This message was sent by Atrenta Inc., 2077 Gateway Place, Suite 300, San Jose CA 95110 USA.
Mail to unsubscribe@atrenta.com if you prefer not to receive future e-mail from Atrenta Inc.