| Archive : Industry News : 2005 |
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| » | A systematic approach to verifying FSMs Nov 17, 2005 By By Shaker Sarwary, Atrenta, and Michael A Beaver, Insilica -- EDN, 10/27/2005 |
| » | Tools enforce best practices in embedded and SystemC design Jun 13, 2005 By EDN |
| » | Atrenta expands RTL analysis and verification May 04, 2005 By EE Times |
| » | Atrenta's Predictive Development Tool Improves Risk/Reward Equation Apr 20, 2005 By NE Asia Online |
| » | Atrenta step toward ESL design - SpyGlass creator rolls out unified IC Physical Planning, design, implementation approach. Apr 08, 2005 By EETimes |
| » | EDA vendor introduces trio of early-prototyping tools - Atrenta's first 1Team package addresses RT-level prototyping Apr 08, 2005 By EDN |
| » | Atrenta goes floorplanning Apr 08, 2005 By Electronics Weekly |
| » | Atrenta announces 'Made in India' EDA software Apr 08, 2005 By EE Times |
| » | Reducing false errors in clock-domain crossing analysis - by Dr. Bernard Murphy, Atrenta Inc. Apr 04, 2005 By EE Design |
| » | Atrenta to expand India presence Apr 04, 2005 By Silicon India |
| » | Opposing Forces - By Ajoy Bose, Atrenta Inc. Apr 04, 2005 By EE Times |
| » | Power, crosstalk crisis to reroute IC design flows Apr 04, 2005 By EE Times |
| » | Functional Analyzer Scopes Out SoC Defects In RTL Apr 04, 2005 By Electronic Design |
| » | 'On shoulders of giants' Apr 04, 2005 By EE Times |
| » | From idea to industry inside track From idea to industry inside track Apr 04, 2005 By EE Times |
| » | Launching offshore. Why-and how-early-stage startups are doing more R&D work in India Apr 04, 2005 By Electronic Business |
| » | Tackling multiple clocks in SoCs - by Sanjay Churiwala, Atrenta Inc. Apr 04, 2005 By EE Times |
| » | Chip design software firm favours IPO Apr 04, 2005 By Electronics Weekly |
| » | Designing for Test at RTL - by Ralph Marlett, Atrenta Inc. Apr 04, 2005 By Embedded World |
| » | FPGAs to ASIC: Prototype to Production Apr 04, 2005 By EDN Magazine |
| » | Predictive analysis for low-power IA designs Apr 04, 2005 By EE Times Asia |
| » | Asic Design Alive and Well in UK Apr 04, 2005 By Electronic Design Europe |
| » | "Emerging Companies - Leading the Recovery" Apr 04, 2005 By Semiconductor Network |
| » | Atrenta offers to customize SpyGlass tool Apr 04, 2005 By EEDesign.com |
| » | RTL tool provider snags $5.3M funding - EE Times Apr 04, 2005 By EE Times |
| » | Atrenta tool scans thousands of flops, targets low-power design Apr 04, 2005 By EE Times Asia |
| » | Concept Engineering Releases Perl/Tk Schematic Visualization Software: Atrenta incorporates the new Nlview PTK Widget into the SpyGlass platform Apr 04, 2005 By Concept Engineering |
| » | Constraint checking added to chip design Apr 04, 2005 By Electronics Weekly |
| » | Lint tool checks constraint files Apr 04, 2005 By EE Times |
| » | Executive Roundtable: Design Horror Stories Apr 04, 2005 By Electronic News |
| » | Moving DFT to RTL Overcomes Test Vector Issues - by Ralph Marlett, Atrenta Inc. Apr 04, 2005 By EE Times |
| » | US start-up making IP integration more reliable Apr 04, 2005 By Electronics Weekly |
| » | Japan duo tell Asic customers to use SpyGlass chip analysis EDA software Apr 04, 2005 By David Manners in Monterey |
| » | Agere has selected Atrenta's SpyGlass, the industry's only predictive analyser, as its ASIC handoff tool Apr 04, 2005 By ElectronicsTalk |
| » | Use SpyGlass Predictive Analysis for Effective RTL Coding Apr 04, 2005 By by Bhanu Kapoor, Technology Director, Atrenta Inc. - Xcell Journal |
| » | ASIC handoff gets physical as front and back ends coverage Apr 04, 2005 By Electronic Design |
| » | The "BIST" Thing That Happened to SoC Design by Philip George, Atrenta & James Fujimoto, LogicVision Apr 04, 2005 By EDAVision.com |
| » | Atrenta adds logical prototyping to analysis tool Apr 04, 2005 By EEDesign.com |
| » | Putting the "D" Back into Design for Test by Ralph Marlett, Atrenta Inc. Apr 04, 2005 By EDAVision.com |
| » | Slow and steady - Ajoy Bose took his time becoming an entrepreneur Apr 04, 2005 By San Jose Business Journal |
| » | Time to Automate Reuse Policies by Ghulam Nurie, Atrenta Inc Apr 04, 2005 By Electronic News |
| » | What's required for golden RTL? by Ghulam Nurie, Atrenta Inc Apr 04, 2005 By EEDesign.com |
| » | True RTL analysis tool identifies testability issues Apr 04, 2005 By Electronic Products |
| » | Enhanced RTL Prediction Tool Adds Testability Analysis Apr 04, 2005 By TechOnLine |
| » | Atrenta focus on distribution Apr 04, 2005 By EETimes UK |
| » | VC, One of Many, Takes Shine to EDA Apr 04, 2005 By Electronic News |
| » | Predictive-analysis tool finds testability issues at RTL Apr 04, 2005 By Test & Measurement World |
| » | Analysis tool checks structure of RTL code Apr 04, 2005 By Electronics Talk |
| » | Avoiding Design Snafus Apr 04, 2005 By InfoWorld |
| » | Analysis tool checks testability of RTL code Apr 04, 2005 By Electronics Talk |
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