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Archive : Industry News : 2008
 
»Power Opto and Linting in CatapultC and SpyGlass Dec 18, 2008 By DeepChip
»Esterel Studio 6.1 brings first verification methodology handbook to ESL synthesis Dec 16, 2008 By Esterel
»Getting clock-domain crossings right: some notes from the real world Oct 27, 2008 By EDN
»When silicon processes shrink, test needs expand Oct 09, 2008 By soccentral
»Measuring quality in semiconductor IP Sep 30, 2008 By EDA Designline
»Tensilica joins Atrenta's SpyLinks partner program Sep 30, 2008 By Tensilica
»Automating low-power design - A progress report by SCDSource Sep 04, 2008 By SCDSource
»Design challenges increase at 40nm Jun 27, 2008 By DACeZine
»Atrenta announces 1Team-Genesis, collaborates with STMicroelectronics Jun 19, 2008 By EDN
»ST and MediaTek manage media SoC designs Jun 11, 2008 By EDN
»ST Touts certified reference design flow Jun 11, 2008 By EDN
»STMicroelectronics announces certified design flow to accelerate creation of next-generation silicon Jun 09, 2008 By ST
»Preserving the intent of timing constraints May 20, 2008 By EDA DesignLine
»Critical clock-domain-crossing bugs Apr 02, 2008 By EDN
»Power formats: you can have it your way Mar 26, 2008 By Electronic Design
»Online tutorial available for Si2's common power format Feb 18, 2008 By BusinessWire
»Power-intent standards vie for designers' loyalties Feb 18, 2008 By Electronic Design
»Three views on verification challenges Feb 06, 2008 By ChipDesignMag
»An RTL solution to test integration challenges Feb 06, 2008 By SCDSource
 

 
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