Atrenta SpyGlass® Flow for FPGA

While ASICs give the highest performance at a low unit cost, rising mask and NRE costs are making it very difficult to justify an ASIC for low unit volumes. FPGAs offer a low risk, quick time to market solution. There are no significant NRE costs associated with an FPGA design. FPGA designs are becoming highly complex - as complex as ASIC designs.

The SpyGlass solution is an industry leader in providing an RTL analysis platform for Early Design Closure® for ASICs world-wide. The same solution has now been extended to FPGA design.

For FPGA hard or soft IP development and handoff teams, Atrenta works with vendors to establish their IP development flows using SpyGlass.

For the end-customers doing FPGA SoC design, Atrenta has established flows with vendors to provide a working SpyGlass solution.

Please click on the links below for details of vendor flow support: