"At Orise Tech, we specialize in development of Flat Panel Display drivers and controllers. Our customers
demand the highest quality ICs with the latest technology on a regular basis. SpyGlass provides an
efficient working environment for design analysis and debug, greatly improving our designers' productivity."
Vice President of R&D
"At Kodak Alaris, we specialize in providing innovative imaging products to our customers on a
frequent basis. Productivity is key to meeting our schedules. With SpyGlass advanced CDC checks,
we not only meet our schedules for complex designs, but we do it with higher confidence."
Design and Verification Engineer
"At Mediatek, we are committed to very high test coverage to ensure the highest possible
quality products. By adding SpyGlass DFT to our workflow, we have seen increases in our test
coverage while finding problems very early in our flow. This has allowed us to meet our test
quality goals, aggressive schedules and customer demands."
Corporate Vice President
"At Sonics, we are committed to the highest quality standards for our IP.
By adding SpyGlass Constraints to our fully automated verification environment,
we will be able to provide our customers the peace of mind that goes with our joint quality effort."
Chien-Chun (Joe) Chou
Vice President of Engineering
"BugScope is an important part of Altera's robust coverage-driven functional verification methodology.
BugScope allows us to generate numerous high-quality assertions so we can quickly enhance our tests to
reach the highest levels of functional and assertion coverage for our designs."
Principal verification architect
We have three designs in advanced phase of development that rely on inserting memory test with the
SpyGlass MBIST solution. This automatic solution becomes necessary in devices having huge proliferation
of memory instances, as our applications require improving efficiency/lead time in our DFT design flow."
Design Director for the Communication Infrastructure Division
"The Atrenta SpyGlass CDC product provides detailed clock domain synchronization checking,
useful for external IP and IP integration verification. We are pleased to adopt this EDA tool
to assist us with product development efficiencies."
Vice President of Engineering
"BugScope automatically generates high quality assertions which capture the functional constraints in
our RTL, and the tool also identifies the coverage holes we need to patch in our simulation testbench. By
utilizing the BugScope assertion synthesis product as part of our functional verification flow, we are able to
find corner-case bugs and ensure the success of our projects."
Director of Engineering
Entropic Communications, Inc.
"Atrenta's SpyGlass CDC product is critical in helping us avoid design iterations and general
risks associated with our complex designs. We have been very impressed by the comprehensive solution
offered by SpyGlass CDC, which allows us to quickly identify real problems in our clock networks at
the earliest possible point in the design flow..."
Manager Hardware Development - Graphics Competence Center
Fujitsu Microelectronics Europe
"Our advanced digital television chips require automated assembly and sophisticated I/O support.
We are pleased with the results we have seen so far using Atrenta's [GenSys]. We plan to use the product for
automated assembly and I/O configuration on our latest designs."
Dr. Kang, Yong-Seok
Principal Engineer of Design Technology Part
"The integration of Atrenta's SpyGlass MBIST solution in our front-end design kit
has automated ST's proprietary embedded memory test and repair capabilities at RTL. The solution not only allows
early and faster validation at RTL, but also allows timing optimization of the complete RTL with memory BIST
where area impact is known early."
Memory Test Solutions Manager within Central CAD & Design Solutions
"TSMC places high importance on the quality of deliverables from our IP ecosystem.
We have worked closely with Atrenta to refine the process of validating the delivered quality of
soft IP from our ecosystem partners. The capability we are now putting into production is expected
to provide valuable information regarding soft IP quality for our end customers."
Director, Design Infrastructure Marketing Division
"Mentor is dedicated to providing the best possible low-power design and verification tools
to drive our customer's success. The cooperation with Atrenta is significant for Mentor and our customers
to make sure that power issues get resolved early in the design cycle."
Vice President and General Manager, Mentor Emulation Division
"By using SpyGlass-Power for RTL level analysis and efficient clock gating,
we were able to reduce power by up to 40% in our wireless chip."
Department Manager, Device Platform Development Department 1st SoC Operations Unit
"Following our rigorous process to ensure that the assertions and coverage properties
BugScope generated were of high quality, Nvidia qualified BugScope as part of its functional
verification methodology. We look forward to expanding adoption of BugScope across our GPU designs."
Director of Hardware Engineering
"BugScope offers a unique technology that creates high valued assertions and enables our ABV flow."
PLX Technology, Inc.
(STMicroelectronics) had been looking for a design environment ... focusing initially on architectural-level
power analysis, estimation and management, and subsequently on top-down timing budgeting. We were very happy
to discover a clear vision match with Atrenta's [GenSys] product."
Vice President for Central CAD & Design Solutions
"Atrenta's latest release of power and deep submicron test solutions for RTL power estimation,
reduction and verification offer the right answer to address today's complex design challenges.
The version 5.0 of the STARCAD-CEL Reference Flow includes Atrenta's SpyGlass Power and SpyGlass
DFT DSM solutions, enabling our customers to find killer bugs and implement low power design strategies
while saving multiple iterations of synthesis and tens of hours of power simulations at the gate level."
Vice President and General Manager, R&D Department-2
"The soft IP9000 program has already had a positive impact on the delivered quality
of soft IP for TSMC's customers. The addition of physical implementation information and formal
lint analysis will further enhance the effectiveness of the program. The beta test program went very smoothly.
IP Kit 2.0 installed easily and ran with minimal issues during the beta test period for our selected soft
IP alliance partners."
Senior Director, Design Infrastructure Marketing Division
"Atrenta's SpyGlass enables us to gauge quickly the quality of incoming RTL designs from our customers,
reduce risks (e.g. effort and time) and then plan project resources and timelines accordingly. For our complex
SoC designs, the clock domain crossing [CDC] capabilities in SpyGlass have proven to be mission critical."
Head of Embedded Systems Design
"With verification taking as much as 70% of total design cycle time, we believe that verification
at the early stages of design can provide significant improvement in productivity. With SpyGlass AuoVerify,
we were able to identify deeper RTL issues using formal technologies which are hard-to-find using basic
linting or a simulation based methodology. SpyGlass AutoVerify enables us to check 'RTL activation status,'
such as checking dead code, FSM deadlocks, unreachable states, static registers and initialized values
Senior Engineer, Development Dept.II, System Logic Development Center
Fujitsu Kyushu Network Technologies Limited
"Atrenta's SpyGlass platform has been instrumental in helping us reach the stringent quality goals we set
for our broad IP portfolio."
Senior Director of Engineering
"Developing assertions manually was a slow process. It took us roughly 8 man-hours to
write and debug each assertion...In contrast, the BugScope assertion synthesis does all this automatically,
in about 6 minutes, which is a time savings of about 80x"