SpyGlass® DFT has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. Traditional approaches depend on test engineers to design test clocks and set/reset logic for scan insertion at the gate level, where changes can be difficult, time-consuming and expensive. SpyGlass DFT enables users to fine tune testability during RTL creation, when the design impact is greatest and the cost of modifications is lowest. This can significantly shorten development time, reduce cost and improve overall quality.
The test clocks in traditional stuck-at testing are designed to run on the test equipment at frequencies lower than the system speed. At-speed testing requires test clocks to be generated at the system speed, and therefore are often shared with functional clocks from a phase locked loop (PLL) clock source. This additional test clocking circuitry affects functional clock skew, and thus the timing closure of the design. At-speed tests often result in lower than required fault coverage even with full-scan and high (>99%) stuck-at coverage. Identifying reasons for low at-speed coverage at the ATPG stage is too late to make changes to the design and significantly increases schedules. SpyGlass DFT DSM addresses these challenges with advanced timing closure analysis and RTL testability improvements.
Advanced deep submicron designs have hundreds, if not thousands of memories. Testing these memories requires inserting memory built-in self test (MBIST) to achieve high yields. Traditionally, the design is synthesized and then handed over to the ASIC vendor to insert MBIST logic at the netlist level. This approach has several drawbacks:
SpyGlass MBIST has the unique ability to insert MBIST at RTL with any qualified ASIC / memory vendor BIST library components and validate the new connections.Click here to view the SpyGlass MBIST flow
Atrenta's GuideWare Reference methodology provides a structured, easy to use and a comprehensive process for solving RTL design issues, thereby ensuring high quality RTL with fewer design bugs.