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Problem: How do you achieve correct and rapid design implementation? Obvious Approach: - Handoff design intent (RTL and constraints) in a traditional way, with minimal scrutiny for implementation
- Fine tune implementation through expensive, long and multiple iterations with implementation teams
- Expend verification resources for non-domain specific verification tasks (e.g. clock domain crossings)
Atrenta's Rapid Productivity Approach: - Handoff "scrutinized design intent" - RTL (or structural netlist) and constraints which are scrutinized for achievable and predictable implementation
- Accelerate implementation on correct design specification
- Free up verification engineer's time to focus on domain specific verification
Solution: Atrenta Tools & Methodologies Atrenta's SpyGlass suite of tools is a complete, proven solution to achieve design intent closure at the authoring stage. Atrenta tools provide a single-cockpit environment to achieve certification of RTL/Netlist and constraints for predictable implementation. Atrenta tools & methodologies address issues with synthesizability, CDC, power management, constraints management, DFT & area, timing & power estimates.
Early Design Analysis- SpyGlass® Product Family SpyGlass - Early design analysis for logic designers.
SpyGlass-CDC - Industry's most comprehensive, practical, and powerful CDC solution.
SpyGlass-DFT - Design for test at RTL.
SpyGlass-Power - Design for low power at RTL.
SpyGlass-Constraints - Specify constraints early, validate continuously & automate handoff.
Early Implementation- 1Team® Product Family 1Team-Implement - Physical and timing closure at architecture/RTL.
1Team-System - Comprehensive analysis of SystemC. |
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