1Team-Genesis IO
Automated I/O
Generation
Today's complex SoC's include more peripheral interfaces in the core than can be accessed at one time. This requires a complex, yet flexible muxing strategy that allows configuration pins or software running on the system to control which interfaces are accessible at any given time. Consequently, I/O subsystem designers spend a lot of time designing these complex I/O subsystems and then adapting them to inevitable specification changes during the course of a design.
1Team®- Genesis IO provides a platform to address these issues and seamlessly integrate the I/O fabric with the rest of the SoC.
Key Features
- Easily captures and allows review of the I/O specification through interactive entry or tcl commands; Complete SoC I/O layer specification for I/O-cell buffers, configuration control, pin multiplexing, boundary scan and package definition parameters
- Provides per-path definable mux-cells and muxing priority to manage timing-critical paths ? supports input muxing, input deselect muxing and output muxing in both function and test paths
- Automatically generates select logic driven by configuration pins and/or core signals
- Supports user-defined sets of muxed control signals (pull-enable for example) and non-muxed signals (pull-up/down for example)
- Generates bond pad and ball-grid diagrams to enable visualization of pad and ball layout
- Optionally inserts boundary scan cells and stitches the scan chain, under user control.
- Supports multiple cores for flexibility in combining subsystems under a common I/O fabric
- Provides user-guided netlist partitioning to control partitioning of subsystems within the generated logic
- Supports analog and differential paths
- Unique incremental schematic features enable review and debug of the logic cone associated with a single device pin
- Automatically generates I/O fabric RTL in either Verilog or VHDL
- Minimizes opportunities for human error through real-time consistency checking
- Automatically generates assertions and a testbench to validate the generated RTL
- Enables cell library model definition in Tcl or its import from RTL or IP-XACT and augmentation with pin-type information through the GUI or Tcl
Key Benefits
- Proven I/O fabric generation technology that can handle a wide range of I/O architectures, yet reduces the capture task to a common table
- Complete platform for specifying I/O architecture including functional, test and analog paths, pin multiplexing and validation
- Accelerates turn-around time for late changes to the I/O architecture
- Acceerates netlist generation and documentation interfaces as a result of tight integration with the 1Team-Genesis Assembly and Registers solutions
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