Early Physical Feasibility Analysis For IP Developers and SoC Architects

Congestion and routability are major design closure issues hampering today's complex designs at 65nm and below. Congestion affects both the performance (area, timing, power) as well as the yield of the SOC. Typically, congestion used to be handled during back-end implementation. Given the complexity of today's designs and the challenges of nanometer geometries, it has become increasingly harder to fix congestion issues in the back-end. Moreover, late fixes in the back-end create conflicting tradeoffs with area, timing and power and often result in an increase in the die size or a delay in the design tapeout or both. This undesirable situation can be avoided if these congestion issues can be predicted (and prevented) during the early architecture planning and RTL development stages.

The 1Team®-Genesis Physical solution enables SoC architects and RTL designers to explore the physical feasibility of their design rapidly and accurately. IP-level physical analysis helps RTL designers understand the congestion characteristics of their RTL structure and make necessary refinements to their RTL (microarchitecture) before handing off to back-end implementation. SoC-level physical analysis helps architects get early estimates of the die size and package requirements, assess the feasibility of the interconnect from a routability and timing standpoint and make architectural refinements, as necessary. Overall, the 1Team-Genesis Physical solution reduces the number of long iterations required with back-end implementation by providing designers with early insights into the physical characteristics of their design.

• Early physical analysis at RTL
• Congestion scores based on structural analysis of the RTL that help designers understand the congestion characteristics of a particular RTL module
• Strong underlying technology infrastructure enabling multi-dimensional (area, timing, power and clocks) RTL analysis
• Intuitive GUI environment enabling cross-probing from logical, physical and timing reports to the schematic as well as the RTL
• Automatic RTL floorplanning and floorplan metrics give additional physical insights
• Infrastructure for what-if analysis and tradeoffs providing quick impact of possible design changes
• Built-in static timing analysis and power estimation engines
• Built on industry standards: OA, .lib, SDC, LEF/DEF

• Enables early design closure at RTL
• Reduces physical design iterations by over 50%; shortens design cycle
• Provides early analysis & estimates of area, congestion and timing for SoC architects as well as IP designers
• Enables RTL designers to identify structures causing congestion and timing problems and fix them before handing off to implementation
• Enables SoC architects to assess the feasibility of the interconnect and make necessary architectural refinements
• Cross probing accelerates the analyze-debug-fix cycle
• Automatic topology creation accelerates floorplanning of large and complex designs