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Problem: How do you achieve correct and rapid design implementation?
Normal Approach:
- Handoff design intent (RTL and constraints) in a traditional way, with minimal scrutiny for implementation
- Fine tune implementation through expensive, long and multiple iterations with implementation teams
- Expend verification resources for non-domain specific verification tasks (e.g. clock domain crossings)
Atrenta's Early Design Closure® Approach
- Handoff "scrutinized design intent" - RTL (or structural netlist) and constraints which are scrutinized for achievable and predictable implementation
- Accelerate implementation on correct design specification
- Free up verification engineer's time to focus on domain specific verification
Solution: Atrenta Tools & Methodologies
Atrenta's SpyGlass® and GenSys™ product lines form a complete, proven solution to achieve Early Design Closure.
Atrenta tools provide an environment to achieve certification of RTL/Netlist and constraints for predictable implementation.
These product families address issues with architecture capture, IP import and chip assembly, synthesizability, CDC, power management, constraints management,
DFT and area, timing and power estimates.
Atrenta's GuideWare™ reference methodologies allow our Early Design Closure solutions to easily fit into your existing design flows.
RTL Verification & Optimization- SpyGlass® Product Family
SpyGlass - Early design analysis for logic designers.
SpyGlass CDC - Industry's most comprehensive, practical, and powerful CDC solution.
SpyGlass DFT - Design for test at RTL.
SpyGlass Power - Design for low power at RTL.
SpyGlass Constraints - Specify constraints early, validate continuously & automate handoff.
SpyGlass Physical - Early Implementation Readiness Analysis for RTL Blocks
Design Capture & Exploration- GenSys™ Product Family
GenSys Assembly - Architecture capture and chip assembly
GenSys Registers - Automated register management
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