RTL Prototyping for IC Architects, Logic Designers, and Physical Designers

In order to manage a design project and make important trade-offs, the architect and RTL designers need to know timing & physical feasibility of the design at the early-RTL stage. Trying to attain design closure at later stages of the design (at gate-level) is often tedious and sometimes impossible. Debugging the gate-level design bit-by-bit versus driving the solution from RTL, burdens both front end and back end teams.

The 1Team®-Implement solution enables IC architects and RTL designers to explore feasibility of their design rapidly and accurately, and provides directed guidance to modify RTL to achieve design goals. With its unique ability to perform fast, accurate analysis at the RTL level, and visualize issues directly in the RTL, it empowers RTL designers to make high-impact trade-offs earlier in the project. In order to complete the design, the 1Team-Implement solution provides a clean handoff to downstream implementation tools.

In short, the 1Team-Implement solution delivers physical & timing closure at architecture/RTL by providing robust RTL prototyping for IC architects, logic designers, and physical designers.

• Seamless integration of the logical, physical, timing domains for RTL prototyping
• Intuitive GUI environment enables all-way cross-probing to RTL from schematic, logical hierarchy, physical and timing
• Robust technology infrastructure enables RTL prototyping
• Fast and accurate physical synthesis--no traditional WLMs
• Rapid automatic floorplan creation: multimillion-instance designs with large number of hard/soft macros
• Global routing and congestion analysis
• Static timing analysis, with native ILM support
• Built on industry standards: OA, .lib, SDC, LEF/DEF
• Customizable logical, timing, physical, and methodology rule checking
• Supports various hand-off flows: RTL, netlist, or floorplan to downstream implementation tools

• Captures a working specification of the design in early prototypes which evolve with the project
• Provides early analysis & prediction of timing, area and congestion for IC architects and RTL designers
• Enables RTL designers to visualize timing & physical implications in their microarchitectures without requiring physical expertise
• Enables architectural and RTL changes for greater impact on physical & timing implement-ability of the design
• Accelerates floorplanning of large and complex designs
• Empowers user to choose the best of alternate floorplans to hand-off to backend tools
• Delivers physical & timing closure to designers at RTL