Specify Constraints Early, Validate Continuously & Automate Handoff

Creating and ensuring correct and consistent constraints at all levels of the design hierarchy and throughout the design cycle is a vital and increasingly challenging task. The difficulties can include: writing new constraints; managing thousands of lines of legacy constraints; managing thousands of timing exceptions across the design flow; unwanted iterations due to changing constraints; and erroneous constraints resulting in redesigns and even respins.

The SpyGlass®-Constraints solution provides a big productivity boost to IC design efforts by automating the creation, validation and management of constraints. The SpyGlass-Constraints solution generates new constraints where needed and verifies that existing constraints are correct and consistent across all phases of development: pre-synthesis, pre-layout and post-layout.

The SpyGlass-Constraints solution can trim weeks or more from design schedules by pin-pointing the root cause of constraint problem quickly. And by ensuring valid constraints, the SpyGlass-Constraints solution can avert design flaws and costly respins. The solution also helps assure a smoother hand-off between tools in multi-vendor flows. In addition, advanced options greatly streamline one of the most complex of constraints management tasks by automating timing exception generation and verification.

The SpyGlass-Constraints solution automatically generates new constraints from RTL or netlists, based on the topology of the design. It identifies clocks--including generated clocks--and ties all inputs to the correct clocks. The SpyGlass-Constraints solution understands multiplexed inputs, identifies clock domain crossings and generates false path constraints at those crossings.

The SpyGlass-Constraints solution checks new constraints and legacy constraints against RTL and netlists to verify correctness and completeness at each stage. The SpyGlass-Constraints solution also checks for consistency among constraints--e.g., between multiple block-level constraints and between block- and top-level constraints. The SpyGlass-Constraints solution also understands complex case analysis in order to make sure that all modes are addressed, within and across constraints files for different modes and corners.

The SpyGlass-Constraints solution offers options that greatly simplify the difficult task of timing exception management. The Timing Exception Verification (TXV) option automatically verifies the correctness of exceptions that designers have previously specified. Using sophisticated analytics, both options examine the RTL and automatically detect functional false paths and multicycle paths. The Timing Exception Generation (TXG) option automatically generates timing critical exceptions that improve the chip quality of results during implementation.

The SpyGlass-Constraints solution methodology provides a structured, easy to use and a comprehensive method for solving constraint problems that ensures quality results with fewer but meaningful violations, thus saving time.

• Provides methodology documentation and rule-sets as part of the product
• Walks users through a series of recommended steps to optimize constraints at block level, as well as, chip level constraints at RTL, pre-layout and post-layout stages - the steps include design setup, creating new SDC components, cleaning clock and delay constraints, fixing timing exceptions, resolving hierarchical constraints, and creating timing-critical timing exceptions post-static timing analysis

• Automatically creates and verifies constraints
• Ensures that constraints are correct and consistent throughout the design flow, from RTL through floorplanning
• Validates consistency and correctness at all levels: chip-to-block and block-to-block
• Can save weeks or months of manual creation and verification
• Simplifies management of legacy constraints
• Prevents design errors and respins
• Results in better-optimized silicon
• Supports RTL and netlist input
• Supports full Tcl-based SDC, compliant with DesignCompiler, PrimeTime and BlastFusion constraints formats
• Flags redundant and over-specified constraints
• Advanced options automate timing exception generation and verification